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ADC12DL040

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

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AC Electrical Characteristics

(1) (2) (3) (4)

Typical

Limits

Units

Symbol

Parameter

Conditions

(5)

(5)

(Limits)

Maximum Clock Frequency

40

MHz (min)

Minimum Clock Frequency

10

MHz

Clock High Time

Duty Cycle Stabilizer On

12.5

5

ns (min)

Clock Low Time

Duty Cycle Stabilizer On

12.5

5

ns (min)

Clock Rise and Fall Times

Duty Cycle Stabilizer On

2

4

ns (max)

Clock High Time

Duty Cycle Stabilizer Off

12.5

10

ns (min)

Clock Low Time

Duty Cycle Stabilizer Off

12.5

10

ns (min)

Clock Rise and Fall Times

Duty Cycle Stabilizer Off

2

ns (max)

Conversion Latency

Parallel mode

7

Clock Cycles

3.5

ns (min)

Data Output Delay after Rising Clock

Parallel mode

6.0

Edge

9.6

ns (max)

Conversion Latency

Multiplex mode, Channel A

7.5

Clock Cycles

Conversion Latency

Multiplex mode, Channel B

8

Clock Cycles

3.5

ns (min)

Data Output Delay after Clock Edge

Multiplex mode

6.0

9

ns (max)

ABb to Data Skew

±0.5

ns (max)

Aperture Delay

2

ns

Aperture Jitter

1.2

ps rms

Data outputs into Hi-Z Mode

10

ns

Data Outputs Active after Hi-Z Mode

10

ns

1.0 µF on pins 4, 14; 0.1 µF on pins

Power Down Mode Exit Cycle

5,6,12,13; 10 µF between pins 5, 6 and

1

µs

between pins 12, 13

(1)

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

conversions.

(2)

(3)

(4)

(5)

Quality Level).

10

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