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66AK2E05XABDA25 Datasheet(PDF) 2 Page - Texas Instruments |
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66AK2E05XABDA25 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 282 page  66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 www.ti.com • System Resources – Five Enhanced Direct Memory Access (EDMA) Modules – Three On-Chip PLLs • Commercial Case Temperature: – SmartReflex Automatic Voltage Scaling – 0ºC to 85ºC – Semaphore Module • Extended Case Temperature: – Thirteen 64-Bit Timers – -40ºC to 100ºC 1.2 Applications • Avionics and Defense • Servers • Communications • Enterprise Networking • Industrial Automation • Cloud Infrastructure • Automation and Process Control 1.3 KeyStone II Architecture TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC and DSP processing cores along with both hardware/firmware based application-specific acceleration and high performance I/Os. The KeyStone II Multicore Architecture is a proven device architecture to achieve the full performance entitlement through the following major components: TeraNet, Multicore Shared Memory Controller, Multicore Navigator, and HyperLink. TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple duplex communication channels in parallel between the master and slave ports without interference. The priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system. The Multicore Shared Memory Controller (MSMC) is the center of the KeyStone II memory architecture. It provides multiple fast and high-bandwidth channels for processor cores to access DDR and minimizes the access latency by directly connecting to the DDR. The MSMC also provides the flexibility to expand processor cores with little impact at the device level. In addition, it provides multi-bank based fast on-chip SRAM shared among processor cores and IOs. It also provides the I/O cache coherency for the device when the Cortex-A15 processor core is integrated. The Multicore Navigator provides a packet-based IPC mechanism among processing cores and packet based peripherals. The hardware-managed queues supports multiple-in-multiple-out mode without using mutex. Coupled with the packet-based DMA, the Multicore Navigator provides a highly efficient and software-friendly tool to offload the processing core to achieve other critical tasks. HyperLink provides a 50-GBaud chip-level interconnect that allows devices to work in tandem. Its low latency, low overhead and high throughput makes it an ideal interface for chip-to-chip interconnections. There are two generations of KeyStone architecture. The 66AK2E0x device is based on KeyStone II, which integrates a Cortex-A15 processor CorePac. 1.4 Device Description The 66AK2E0x is a high performance device based on TI's KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor single-core or quad-core CorePac and C66x DSP core, that can run at a core speed of up to 1.4 GHz. TI's 66AK2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation. TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), C66x CorePac, network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling. 2 66AK2E0x Features and Description Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: 66AK2E05 66AK2E02 |
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