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ZL30407QCC1 Datasheet(PDF) 8 Page - Zarlink Semiconductor Inc |
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ZL30407QCC1 Datasheet(HTML) 8 Page - Zarlink Semiconductor Inc |
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8 / 57 page  ZL30407 Data Sheet 8 Zarlink Semiconductor Inc. 20 F8o Frame Pulse ST-BUS/GCI 8.192 Mbps (CMOS tristate output). This is an 8 kHz, 122 ns, active high framing pulse, which marks the beginning of a ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192 Mbps. See Figure 18 for details. 21 E3DS3/OC3 E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output (pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155 clock outputs (high impedance) and sets C34/C44 output to provide C34 and C44 clocks. In Software Control connect this pin to ground. 22 E3/DS3 E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44 output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and logic high selects 8.592 MHz clock. Connect this input to ground in Software Control. 23 SEC Secondary Reference (Input). This input is used as a secondary reference source for synchronization. The ZL30407 can synchronize to the falling edge of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz clock. In Hardware Control, selection of the input reference is based upon the RefSel control input. This pin is internally pulled up to VDD. 24 PRI Primary Reference (Input). This input is used as a primary reference source for synchronization. The ZL30407 can synchronize to the falling edge of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz clock. In Hardware Control, selection of the input reference is based upon the RefSel control input. This pin is internally pulled up to VDD. 25 GND Ground 26 IC Internal Connection. Leave unconnected. 27 GND Ground 28 AVDD Positive Analog Power Supply. Connect this pin to VDD. 29 VDD Positive Power Supply 30 31 C155N C155P Clock 155.52 MHz (LVDS output). Differential outputs for the 155.52 MHz clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or they can be disabled by applying logic high. In the disabled state the LVDS outputs are internally terminated with an integrated 100 Ω resistor (two 50Ω resistors connected in series). The middle point of these resistors is internally biased from a 1.25 V LVDS bias source. 32 GND Ground 33 NC No internal bonding Connection. Leave unconnected. Pin Description (continued) Pin # Name Description |
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