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ZL30407QCC Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL30407QCC Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
10 / 57 page ZL30407 Data Sheet 10 Zarlink Semiconductor Inc. 49 VDD Positive Power Supply 50 NC No internal bonding Connection. Leave unconnected. 51 C20i Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master Clock Oscillator. The clock oscillator should be connected directly (not AC coupled) to the C20i input and it must supply clock with duty cycle that is not worse than 40/60%. 52 GND Digital Ground 53 C34/C44 Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3 applications) when E3DS3/OC3 is high, or to be either 8.592 MHz or 11.184 MHz when E3DS3/OC3 is low. See description of E3DS3/OC3 and E3/DS3 inputs for details. In Software Control the functionality of this output is controlled by Control Register 2 (Table 8 "Control Register 2 (R/W)"). 54 VDD Positive Power Supply 55 HOLDOVER Holdover Indicator (CMOS output). Logic high at this output indicates that the device is in Holdover mode. 56 NC No internal bonding Connection. Leave unconnected. 57 LOCK Lock Indicator (CMOS output). Logic high at this output indicates that ZL30407 is locked to the input reference. See LOCK bit description in Status Register 1 and Section 2.2.4, Lock Indicator (LOCK) for details. 58 NC No internal bonding Connection. Leave unconnected. 59 DS Data Strobe (5 V tolerant input). This input is the active low data strobe of the processor interface. 60 IC Internal Connection. Connect to ground. 61 SECOR Secondary Reference Out of Range (Output). Logic high at this pin indicates that the Secondary Reference is off the PLL centre frequency by more than ±12 ppm. These thresholds support Stratum 3 applications. See SECOR bit description in Status Register 1 for details. 62 OE Output Enable (Input). Logic high on this input enables C19, F16, C16, C8, C6, C4, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output clocks pins into a high impedance state. 63 CS Chip Select (5 V tolerant input). This active low input enables the microprocessor interface. When CS is set to high, the microprocessor interface is idle and all Data Bus I/O pins will be in a high impedance state. Pin Description (continued) Pin # Name Description |
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