SN65HVD05,SN65HVD06, SN65HVD07

SN75HVD05, SN75HVD06, SN75HVD07

SLLS533B – MAY 2002 – REVISED MAY 2003

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8

Input

Generator

50

Ω

3 V

VO

S1

1.5 V

1.5 V

tPLZ

2.3 V

0.5 V

≈ 3 V

0 V

VOL

VI

VO

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

RL = 110 Ω

± 1%

CL = 50 pF ±20%

CL Includes Fixture

andInstrumentation

Capacitance

D

A

B

DE

VI

tPZL(1 & 2)

VCC

VCC

Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

VID

VA

VB

IO

A

B

IB

VO

R

IA

VIC

VA + VB

2

Figure 7. Receiver Voltage and Current Definitions

Input

Generator

50

Ω

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

VO

1.5 V

0 V

1.5 V

1.5 V

3 V

VOH

VOL

1.5 V

10%

1.5 V

tPLH

tPHL

tr

tf

90%

VI

VO

CL = 15 pF ±20%

CL Includes Fixture

andInstrumentation

Capacitance

A

B

RE

VI

R

0 V

90%

10%

Figure 8. Receiver Switching Test Circuit and Voltage Waveforms