IDT72V241L15PFI datasheet(4/14 Pages) IDT

Part #	IDT72V241L15PFI

Description	3.3 VOLT CMOS SyncFIFO??256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*Includes jig and scope capacitances.

AC TEST CONDITIONS

In Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

OutputReferenceLevels

1.5V

OutputLoad

See Figure 1

or equivalent circuit

Figure 1. Output Load

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 3.3 ±0.3V, TA = 0

°C to + 70°C;Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C)

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Industrial temperature range is available by special order for speed grades faster than 15ns.

3. Values guaranteed by design, not currently tested.

Commercial

Com'l & Ind'l(2)

Commercial

IDT72V201L10

IDT72V201L15

IDT72V201L20

IDT72V211L10

IDT72V211L15

IDT72V211L20

IDT72V221L10

IDT72V221L15

IDT72V221L20

IDT72V231L10

IDT72V231L15

IDT72V231L20

IDT72V241L10

IDT72V241L15

IDT72V241L20

IDT72V251L10

IDT72V251L15

IDT72V251L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

100

—

66.7

—

50

MHz

tA

Data Access Time

2

6.5

2

10

2

12

ns

tCLK

Clock Cycle Time

10

—

15

—

20

—

ns

tCLKH

Clock High Time

4.5

—

6

—

8

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

8

—

ns

tDS

DataSetupTime

3

—

4

—

5

—

ns

tDH

Data Hold Time

0.5

—

1

—

1

—

ns

tENS

Enable Setup Time

3

—

4

—

5

—

ns

tENH

Enable Hold Time

0.5

—

1

—

1

—

ns

tRS

Reset Pulse Width(1)

10

—

15

—

20

—

ns

tRSS

ResetSetupTime

8

—

10

—

12

—

ns

tRSR

Reset Recovery Time

8

—

10

—

12

—

ns

tRSF

Reset to Flag and Output Time

—

10

—

15

—

20

ns

tOLZ

Output Enable to Output in Low-Z(3)

0—

0

—

0—

ns

tOE

Output Enable to Output Valid

3

—

3

8

3

10

ns

tOHZ

Output Enable to Output in High-Z(3)

3—

3

8

310

ns

tWFF

Write Clock to Full Flag

—

6.5

—

10

—

12

ns

tREF

Read Clock to Empty Flag

—

6.5

—

10

—

12

ns

tAF

Write Clock to Almost-Full Flag

—

6.5

—

10

—

12

ns

tAE

Read Clock to Almost-Empty Flag

—

6.5

—

10

—

12

ns

tSKEW1

Skew time between Read Clock & Write

5

—

6

—

8

—

ns

Clock for Empty Flag &Full Flag

tSKEW2

Skew time between Read Clock & Write

14

—

18

—

20

—

ns

Clock for Almost-Empty Flag &

Almost-Full Flag

30pF*

D.U.T.

4092 drw03

3.3V

330

Ω

510

Ω

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