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IDT72V201L15JI Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72V201L15JI Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 14 page 10 IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES NOTE: 1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO. Figure 8. Full Flag Timing NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary ( EF = LOW). Figure 9. Empty Flag Timing tSKEW1 tDS tSKEW1 tENH tENH NEXT DATA READ DATA READ WCLK D0 - D8 FF WEN1 WEN2 (If Applicable) RCLK REN1, REN2 Q0 - Q8 tWFF tWFF tWFF tENS tENS DATA IN OUTPUT REGISTER OE LOW NO WRITE NO WRITE 4092 drw10 tA tA tENS tENS tENS (1) tENS (1) tENH tENH NO WRITE tA tDS tDS DATA WRITE 1 tENS tENH tENH tENS tENH tENS tENH DATA WRITE 2 WCLK D0 - D8 RCLK EF REN1, REN2 OE Q0 - Q8 DATA READ tSKEW1 (1) tFRL tFFL DATA IN OUTPUT REGISTER (1) tSKEW1 LOW tENS WEN2 (If Applicable) tREF tREF tREF WEN1 4092 drw11 |
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