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IDT72V211L15J Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72V211L15J Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 14 page 1 3.3 VOLT CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT72V201, IDT72V211 IDT72V221, IDT72V231 IDT72V241, IDT72V251 ©2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4092/2 FEBRUARY 2002 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES clocked read and write controls. The architecture, functional operation and pin assignments are identical to those of the IDT72201/72211/72221/72231/ 72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and 3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of databufferingneedssuchasgraphics,localareanetworksandinterprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two Write Enable pins ( WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the Write Enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two Read Enable pins ( REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual- clock operation. An Output Enable pin ( OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty ( EF) and Full (FF). Two programmable flags, Almost-Empty ( PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting the Load pin ( LD). These FIFOs are fabricated using IDT's high-speed submicron CMOS technology. FEATURES: ••••• 256 x 9-bit organization IDT72V201 ••••• 512 x 9-bit organization IDT72V211 ••••• 1,024 x 9-bit organization IDT72V221 ••••• 2,048 x 9-bit organization IDT72V231 ••••• 4,096 x 9-bit organization IDT72V241 ••••• 8,192 x 9-bit organization IDT72V251 ••••• 10 ns read/write cycle time ••••• 5V input tolerant ••••• Read and Write clocks can be independent ••••• Dual-Ported zero fall-through time architecture ••••• Empty and Full Flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags can be set to any depth ••••• Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively ••••• Output Enable puts output data bus in high-impedance state ••••• Advanced submicron CMOS technology ••••• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin plastic Thin Quad FlatPack (TQFP) ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available DESCRIPTION: TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™ are very high-speed, low-power First-In, First-Out (FIFO) memories with FUNCTIONAL BLOCK DIAGRAM WCLK WEN1 WEN2 D0 - D8 LD OFFSET REGISTER INPUT REGISTER RAM ARRAY 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER OE RS Q0 - Q8 RCLK REN1 REN2 READ CONTROL LOGIC READ POINTER FLAG LOGIC EF PAE PAF FF 4092 drw 01 |
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