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AD1981B Datasheet(PDF) 12 Page - Analog Devices

Part # AD1981B
Description  AC ??7 SoundMAX Codec
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1981B Datasheet(HTML) 12 Page - Analog Devices

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REV. B
AD1981B
–12–
Mono Volume Register (Index 06h)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
06h
Mono Volume
MVM
X
X
X
X
X
X
X
X
X
X
MV4
MV3
MV2
MV1
MV0
8000h
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table II for examples. This register controls the mono output volume and mute bit. The volume register contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,
whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all
lower five bits will read 1s whenever this bit is set to 1.
MV[4:0]
Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a
maximum attenuation of 46.5 dB.
MVM
Mono Volume Mute. When this bit is set to 1, the channel is muted.
Table II. Volume Settings for Mono
Control Bits D[4:0] for Mono (06h)
D15
WRITE
READBACK
Function
0
0000
0 0000
0 dB Gain
00 1111
0 1111
–22.5 dB Gain
01 1111
1 1111
–46.5 dB Gain
1x xxxx
x xxxx
– dB Gain, Muted
x in the above table is a wild card and has no effect on the value.
PHV[4:0]
Phone Volume. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The
LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute bit enabled.
PHM
Phone Mute. When this bit is set to 1, the phone channel is muted.
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
Phone Volume Register (Index 0Ch)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0Ch Phone Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4
PHV3
PHV2
PHV1
PHV0
8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.


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