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ZN448E Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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3 / 18 page ZN448/9 3 ELECTRICAL CHARACTERISTICS (Cont.) V IN = +4V, VCC = MAX V IN = +0.8V, VCC = MAX V IN = +2.4V, VCC = MAX V IN = +0.4V, VCC = MAX V IN = +2.4V, VCC = MAX V IN = +0.4V, VCC = MAX I OH = +2.4V, VCC = MAX I OL = +0.4V, VCC = MAX V OUT = +2V - - - 0.9 500 4 - - - 2 - - - 2 - - - 2.4 - - - - - - 180 60 80 60 200 - - +0.5 - - - - - - - - - 300 ±10 - - +150 -300 - - - - - - 180 210 80 110 80 - - 1 - 2 1 - - 0.8 800 -500 - 0.8 - - - 0.8 - - - 0.4 -100 1.6 2 -1.5 250 260 100 140 100 - 250 Min. Typ. Max. MHz %/ °C k Ω MHz ns V V µA µA V V µA µA V V µA µA V V µA mA µA V ns ns ns ns ns ns ns Parameter Units Conditions Clock On-chip clock frequency Clock frequency temperature coefficient Clock resistor Maximum external clock frequency Clock pulse width High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL Logic (over operating temperature range) Convert input High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL RD input High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL High level output voltage VOH Low level output voltage VOL High level output current IOH Low level output current IOL Three-state disable output leakage Input clamp diode voltage RD input to data output Enable/disable delay times TE1 TE0 TD1 TD0 Convert pulse width tWR WR input to BUSY output GENERAL CIRCUIT OPERATION The ZN448/9 utilises the successive approximation technique. Upon receipt of a negative-going pulse at the WR input the BUSY output goes low, the MSB is set to 1 and all other bits are set to 0, which produces an output voltage of V REF/2 from the DAC. This is compared to the input voltage VIN; a decision is made on the next negative clock edge to reset the MSB to 0 if < V IN or leave it set to 1 if < V IN. Bit 2 is set to 1 on the same clock edge, producing an output from the DAC of or + depending on the state of the MSB. This voltage is compared to V IN and on the next clock edge a decision is made regarding bit 2, whilst bit 3 is set to 1. This procedure is repeated for all eight bits. On the eighth negative clock edge BUSY goes high indicating that the conversion is complete. V REF 2 V REF 2 V REF 4 V REF 2 V REF 4 During a conversion the RD input will normally be held high to keep the three-state buffers in their high impedance state. Data can be read out by taking RD low, thus enabling the three-state output. Readout is non-destructive. CONVERSION TIMING The ZN448/9 will accept a low-going CONVERT pulse, which can be completely asynchronous with respect to the clock, and will produce valid data between 7.5 and 8.5 clock pulses later depending on the relative timing of the clock and CONVERT signals. Timing diagrams for the conversion are shown in Fig.3. The converter is cleared by a low-going CONVERT pulse, which sets the most significant bit and results all the other bits and the BUSY flag. Whilst the CONVERT input is low the MSB output of the DAC is continuously compared with the analogue input, but otherwise the converter is inhibited. |
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