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74ACT163SJ Datasheet(PDF) 6 Page - Fairchild Semiconductor |
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74ACT163SJ Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 / 11 page www.fairchildsemi.com 6 AC Operating Requirements for AC Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Note 9: Voltage Range 5.0 is 5.0V ± 0.5V VCC TA = +25°CTA = −40°C to +85°C Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 8) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 3.3 5.5 13.5 16.0 ns Pn to CP 5.0 4.0 8.5 10.5 tH Hold Time, HIGH or LOW 3.3 −7.0 −1.0 −0.5 ns Pn to CP 5.0 −5.0 0 0 tS Setup Time, HIGH or LOW 3.3 5.5 14.0 16.5 ns SR to CP 5.0 4.0 9.5 11.0 tH Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns SR to CP 5.0 −5.5 −0.5 0 tS Setup Time, HIGH or LOW 3.3 5.5 11.5 14.0 ns PE to CP 5.0 4.0 7.5 8.5 tH Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns PE to CP 5.0 −5.0 −0.5 0 tS Setup Time, HIGH or LOW 3.3 3.5 6.0 7.0 ns CEP or CET to CP 5.0 2.5 4.5 5.0 tH Hold Time, HIGH or LOW 3.3 −4.5 0 0 ns CEP or CET to CP 5.0 −3.0 0 0.5 tW Clock Pulse Width (Load) 3.3 3.0 3.5 4.0 ns HIGH or LOW 5.0 2.0 2.5 3.0 tW Clock Pulse Width (Count) 3.3 3.0 4.0 4.5 ns HIGH or LOW 5.0 2.0 3.0 3.5 VCC TA = +25°CTA = −40°C to +85°C Symbol Parameter (V) CL = 50 pF CL = 50 pF Units (Note 9) Min Typ Max Min Max fMAX Maximum Clock Frequency 5.0 120 140 105 MHz tPLH Propagation Delay, CP to Qn 5.0 1.5 5.5 10.0 1.5 11.0 ns (PE Input HIGH or LOW) tPHL Propagation Delay, CP to Qn 5.0 1.5 6.0 11.0 1.5 12.0 ns (PE Input HIGH or LOW) tPLH Propagation Delay 5.0 2.5 7.0 11.5 2.0 13.5 ns CP to TC tPHL Propagation Delay 5.0 3.0 8.0 13.5 2.0 15.0 ns CP to TC tPLH Propagation Delay 5.0 2.0 5.5 9.0 1.5 10.5 ns CET to TC tPHL Propagation Delay 5.0 2.0 6.0 10.0 2.0 11.0 ns CET to TC |
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