5 / 9 page
CY7C168A
5
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
Read Cycle
Write Cycle No. 1 (WE Controlled)
50%
50%
DATA VALID
tRC
tACE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZCE
tPD
CE
HIGH
C168A-6
tWC
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
VCC
SUPPLY
CURRENT
tHZWE
tLZWE
tSD
C168A-7
CE
WE
DATA IN
DATA I/O
ADDRESS
WE
tRCS
tRCH
DATAINVALID
[10, 12]
[9]
Write Cycle No. 2 (CS Controlled)
tWC
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tPWE
tHA
tHD
tHZWE
tSD
ADDRESS
CE
WE
DATA IN
DATA I/O
tSA
C168A-8
DATA IN VALID
[9, 13]
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
