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DAC14135MT Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DAC14135MT Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 12 page 3 http://www.national.com DAC14135 (sample rate = 135MSPS, Tmin = -40°C, Tmax = +85°C, AVDD = +5V, DVDD = +5V, CVDD = +5V, Electrical Characteristics full scale current = 20mA, differential 50Ω doubly terminated output, unless specified otherwise) Absolute Maximum Ratings positive supply voltage (VDD) -0.5V to +6V analog output voltage range -0.7V to +VDD digital input voltage range -0.5V to +VDD output short circuit duration infinite junction temperature 175°C storage temperature range -65°C to 150°C lead solder duration (+300°C) 10sec Note: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Recommended Operating Conditions positive analog supply voltage +5V ±5% positive digital supply voltage +3.3V or +5V ±5% positive clock supply voltage +5V ±5% operating temperature range -40°C to +85°C Package Thermal Resistance Package θ JA θ JC 48-pin TSSOP 56°C/W 16°C/W Package Transistor Count Transistor count 8,600 Ordering Information Model Temperature Range Description DAC14135MT -40°C to +85°C 48-pin TSSOP (industrial temperature range) DAC14135MTX -40°C to +85°C 48-pin TSSOP (TNR 1000 pc reel) DAC14135PCASM Fully loaded evaluation board with DAC14135 … ready for test. CLC5958 Timing Diagram Notes PARAMETERS CONDITIONS TEMP RATINGS UNITS NOTES MIN TYP MAX POWER REQUIREMENTS analog supply current +25°C 28 35 mA 1 digital supply current 135MSPS, DVDD = +5V +25°C 9 15 mA 1 digital supply current 100MSPS, DVDD = +3.3V +25°C 4.5 mA power consumption 135MSPS, DVDD = +5V +25°C 185 mW power consumption 100MSPS, DVDD = +3.3V +25°C 150 mW AVDD power supply rejection ratio at mid-scale +25°C 1.0 %FS/V Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. 1) These parameters are 100% tested at 25°C. 2) These parameters are sample tested at -40°C, +25°C and +85°C. 3) Defined as the net area of undesired output transients in pV-s at a major transition. DAC14135 Timing Diagram N-1 N-2 N N+1 N-1 N D0 – D13 CLOCK T IoutT or IoutF NOTE: 1 clock cycle latency TPD TH TS |
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