COP8CSDR9KMT7 datasheet(3/80 Pages) NSC

Part #	COP8CSDR9KMT7

Description	8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout

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Manufacturer	NSC [National Semiconductor (TI)]

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Table of Contents

1.0 General Description ..................................................................................................................................... 1

2.0 Features ....................................................................................................................................................... 1

3.0 Block Diagram .............................................................................................................................................. 2

4.0 Ordering Information .................................................................................................................................... 2

5.0 Connection Diagrams ................................................................................................................................... 6

6.0 Architectural Overview ............................................................................................................................... 10

6.1 EMI REDUCTION .................................................................................................................................... 10

6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...................................................................... 10

6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................. 10

6.4 TRUE IN-SYSTEM EMULATION ............................................................................................................ 10

6.5 ARCHITECTURE

................................................................................................................................... 10

6.6 INSTRUCTION SET

............................................................................................................................... 10

6.6.1 Key Instruction Set Features ............................................................................................................. 10

6.6.2 Single Byte/Single Cycle Code Execution

....................................................................................... 10

6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................. 10

6.6.4 Bit-Level Control ................................................................................................................................ 11

6.6.5 Register Set ....................................................................................................................................... 11

6.7 PACKAGING/PIN EFFICIENCY .............................................................................................................. 11

7.0 Absolute Maximum Ratings ....................................................................................................................... 12

8.0 Electrical Characteristics ............................................................................................................................ 12

9.0 Pin Descriptions ......................................................................................................................................... 17

9.1 EMULATION CONNECTION ................................................................................................................... 18

10.0 Functional Description .............................................................................................................................. 19

10.1 CPU REGISTERS ................................................................................................................................. 19

10.2 PROGRAM MEMORY ........................................................................................................................... 19

10.3 DATA MEMORY .................................................................................................................................... 19

10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 19

10.4.1 Virtual EEPROM .............................................................................................................................. 20

10.5 OPTION REGISTER ............................................................................................................................. 20

10.6 SECURITY ............................................................................................................................................ 21

10.7 RESET ................................................................................................................................................... 21

10.7.1 External Reset ................................................................................................................................. 22

10.7.2 On-Chip Brownout Reset ................................................................................................................. 22

10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 24

10.8.1 Oscillator .......................................................................................................................................... 24

10.8.2 Clock Doubler .................................................................................................................................. 24

................................................................................................................................................................... 0

10.9 CONTROL REGISTERS ....................................................................................................................... 25

10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 25

10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 25

10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 25

10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 25

10.9.5 T3CNTRL Register (Address X'00B6) ............................................................................................. 26

10.9.6 HSTCR Register (Address X'00AF) ................................................................................................ 26

10.9.7 ITMR Register (Address X'00CF) .................................................................................................... 26

11.0 In-System Programming ........................................................................................................................... 27

11.1 INTRODUCTION ................................................................................................................................... 27

11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 27

11.3 REGISTERS .......................................................................................................................................... 27

11.3.1 ISP Address Registers ..................................................................................................................... 27

11.3.2 ISP Read Data Register .................................................................................................................. 28

11.3.3 ISP Write Data Register ................................................................................................................... 28

11.3.4 ISP Write Timing Register ................................................................................................................ 28

11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 29

11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 29

11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 30

11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 30

11.8 USER ISP AND VIRTUAL E

2

................................................................................................................ 30

11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 32

11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 32

12.0 Timers ....................................................................................................................................................... 34

12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 34

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COP8CSDR9KMT7 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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