TPS70445, TPS70448, TPS70451, TPS70458, TPS70402

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003

10

POST OFFICE BOX 655303

(continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN1/VIN2 terminal

UVLO threshold

2.4

2.65

V

UVLO hysteresis

110

mV

PG1/PG2 terminal

Minimum input voltage for valid PGx

I(PGx) = 300 µA,

V(PGx) ≤ 0.8 V

1.0

1.3

V

Trip threshold voltage

VO decreasing

92%

95%

98%

VO

Hysteresis voltage

Measured at VO

0.5%

VO

tr(PGx)

Rising edge deglitch

30

µs

Output low voltage

VI = 2.7 V,

I(PGx) = 1 mA

0.15

0.4

V

Leakage current

V(PGx) = 6 V

1

µA

EN1/EN2 terminal

High-level ENx input voltage

2

V

Low-level ENx input voltage

0.7

V

Input current (ENx)

–1

1

µA

MR terminal

High-level input voltage

2

V

Low-level input voltage

0.7

V

Pullup current source

6

µA

VOUT1 terminal

Dropout voltage (see Note 4)

IO = 1 A, VIN1 = 3.2 V, TJ = 25°C

160

mV

Dropout voltage (see Note 4)

IO = 1 A, VIN1 = 3.2 V

250

mV

Peak output current

2 ms pulse width

1.2

A

Discharge transistor current

VOUT1 = 1.5 V

7.5

mA

VOUT2 terminal

Peak output current

2 ms pulse width

3

A

Discharge transistor current

VOUT2 = 1.5 V

7.5

mA

FB terminal

Input current – TPS70402

FB = 1.8 V

1

µA

NOTE 4: Input voltage(VIN1 or VIN2) = VO(Typ) – 100 mV. For the 1.5-V, 1.8-V and 2.5-V regulators, the dropout voltage is limited by input voltage

range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test.