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COP8ACC728M8-XE Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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COP8ACC728M8-XE Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 40 page Typical Performance Characteristics (−55˚C ≤ T A = +125˚C) (Continued) Pin Descriptions V CC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset description sec- tion. The device contains two bidirectional (one 8-bit, one 4-bit) I/O ports (G and L), where each individual bit may be inde- pendently configured as a weak pullup input, TRI-STATE (Hi-Z) input or push pull output under program control. Ports G- and L- feature Schmitt trigger inputs. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped reg- isters, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.) Figure 5 shows the I/O port configurations. The DATA and CONFIGU- RATION registers allow for each port bit to be individually configured under software control as shown below: PORT L is a 4-bit I/O port. All L-pins have Schmitt triggers on the inputs. The Port L supports Multi-Input Wake Up on all four pins. The Port L has the following alternate features: L7 MIWU or external interrupt L6 MIWU or external interrupt L5 MIWU or external interrupt L4 MIWU or external interrupt DS012869-34 DS012869-35 DS012869-36 DS012869-37 DS012869-5 FIGURE 5. I/P Port Configurations www.national.com 10 |
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