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COP8SEC516M Datasheet(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP8SEC516M
Description  8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP8SEC516M Datasheet(HTML) 7 Page - National Semiconductor (TI)

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AC Electrical Characteristics
−40˚C
≤ T
A ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
C)
Crystal/Resonator
4.5V
≤ V
CC ≤ 5.5V
1
DC
µs
2.7V
≤ V
CC < 4.5V
2
DC
µs
R/C Oscillator
4.5V
≤ V
CC ≤ 5.5V
3
DC
µs
2.7V
≤ V
CC < 4.5V
6
DC
µs
Frequency Variation (Note 9), (Note 10)
4.5V
≤ V
CC ≤ 5.5V
±15
%
CKI Clock Duty Cycle (Note 9)
fr = Max
45
55
%
Rise Time (Note 9)
fr = 10 MHz Ext Clock
12
ns
Fall Time (Note 9)
fr = 10 MHz Ext Clock
8
ns
EERAM Write Cycle
715
ms
Delay from Power-Up to first EERAM Write
Cycle
65
µs
Output Propagation Delay (Note 8)
t
PD1,tPD0
R
L = 2.2k, CL = 100
pF
SO, SK
4.5V
≤ V
CC ≤ 5.5V
0.7
µs
2.7V
≤ V
CC < 4.5V
1.75
µs
All Others
4.5V
≤ V
CC ≤ 5.5V
1
µs
2.7V
≤ V
CC < 4.5V
2.5
µs
MICROWIRE Setup Time (t
UWS) (Note 12)
20
ns
MICROWIRE Hold Time (t
UWH) (Note 12)
56
ns
MICROWIRE Output Propagation Delay
(t
UPD)(Note 12)
220
ns
Input Pulse Width (Note 9)
Interrupt Input High Time
1
t
C
Interrupt Input Low Time
1
t
C
Timer 1 Input High Time
1
t
C
Timer 1 Input Low Time
1
t
C
Reset Pulse Width
1
µs
Note 3: tC = Instruction cycle time.
Note 4: Maximum rate of voltage change must be < 0.5 V/ms.
Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, G0, and G2–G5 programmed as low out-
puts and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; WATCHDOG and clock monitor disabled. Parameter refers to
HALT mode entered via setting bit 7 of the G Port data register.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.
Note 11: Exclusive of R and C variation.
Note 12: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See
Figure 4 and the MI-
CROWIRE operation description.
Note 13: COP7SER7 Supply Current during Reset will be somewhat higher.
www.national.com
7


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