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QS5LV919133J Datasheet(PDF) 11 Page - Integrated Device Technology |
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QS5LV919133J Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 12 page 11 INDUSTRIALTEMPERATURERANGE QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER tJ SY NC FEEDBACK Q Q0-Q4 Q/2 2xQ Q5 tSKF t SKA LL tSKR tPD AC TIMING DIAGRAM NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at 0.5VDD. |
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