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COPCJ842 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COPCJ842 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 35 page  Memory (Continued) mapped as “registers”, these can be loaded immediately, decremented and tested. Three specific registers: X, B, and SP are mapped into this space, the other registers are avail- able for general usage. Any bit of data memory can be directly set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and indi- vidually set, reset and tested, except the write once only bit (WDREN, WATCHDOG Reset Enable), and the unused and read only bits in CNTRL2 and WDREG registers. Note: RAM contents are undefined upon power-up. Reset EXTERNAL RESET The RESET input pin when pulled low initializes the micro-controller. The user must insure that the RESET pin is held low until V CC is within the specified voltage range and the clock is stabilized. An R/C circuit with a delay 5x greater than the power supply rise time is recommended ( Figure 4). The device immediately goes into reset state when the RE- SET input goes low. When the RESET pin goes high the de- vice comes out of reset state synchronously. The device will be running within two instruction cycles of the RESET pin go- ing high. The following actions occur upon reset: Port L TRI-STATE Port G TRI-STATE Port D HIGH PC CLEARED RAM Contents RANDOM with Power-On- Reset UNAFFECTED with external Reset (power already applied) B, X, SP Same as RAM PSW, CNTRL1, CNTRL2 and WDREG Reg. CLEARED Multi-Input Wakeup Reg. WKEDG, WKEN CLEARED WKPND UNKNOWN Data and Configuration Registers forL&G CLEARED WATCHDOG Timer Prescaler/Counter each loaded with FF The device comes out of the HALT mode when the RESET pin is pulled low. In this case, the user has to ensure that the RESET signal is low long enough to allow the oscillator to re- start. An internal 256 t c delay is normally used in conjunction with the two pin crystal oscillator. When the device comes out of the HALT mode through Multi-Input Wakeup, this de- lay allows the oscillator to stabilize. The following additional actions occur after the device comes out of the HALT mode through the RESET pin. If a two pin crystal/resonator oscillator is being used: RAM Contents UNCHANGED Timer T1 and A Contents UNKNOWN WATCHDOG Timer Prescaler/Counter ALTERED If the external or RC Clock option is being used: RAM Contents UNCHANGED Timer T1 and A Contents UNCHANGED WATCHDOG Timer Prescaler/Counter ALTERED The external RESET takes priority over the Brown Out Re- set. Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out cir- cuit has detected Brown Out condition), the external reset will not oc- cur until the Brown Out condition is removed. External reset has prior- ity only if VCC is greater than the Brown Out voltage. WATCHDOG RESET With WATCHDOG enabled, the WATCHDOG logic resets the device if the user program does not service the WATCH- DOG timer within the selected service window. The WATCH- DOG reset does not disable the WATCHDOG. Upon WATCHDOG reset, the WATCHDOG Prescaler and Counter are each initialized with FF Hex. The following actions occur upon WATCHDOG reset that are different from external reset. WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDFWATCHDOG Underflow bitUNCHANGED Additional initialization actions that occur as a result of WATCHDOG reset are as follows: Port L TRI-STATE Port G TRI-STATE Port D HIGH PC CLEARED RAM Contents UNCHANGED/RANDOM B, X, SP UNCHANGED PSW, CNTRL1 and CNTRL2 (except WDUDF Bit) Registers CLEARED Multi-Input Wakeup Registers WKEDG, WKEN CLEARED WKPND UNKNOWN Data and Configuration Registers forL&G CLEARED WATCHDOG Timer Prescalar/Counter each loaded with FF DS011208-51 RC > 5 x Power Supply Rise Time FIGURE 4. Recommended Reset Circuit www.national.com 11 |
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