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MC9328MX1CVM15 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC9328MX1CVM15 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 96 page  MC9328MX1 Advance Information, Rev. 4 8 Freescale Semiconductor Signals and Connections TCK Test Clock to synchronize test logic and control register access through the JTAG port. TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK. System BIG_ENDIAN BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is a static pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If it is driven logic-low the memory system is configured into little endian. The pin is not supposed to be changed on the fly. ETM ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETMPIPESTAT [2:0] ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. ETMTRACEPKT [7:0] ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] Sensor port data CSI_MCLK Sensor port master clock CSI_VSYNC Sensor port vertical sync CSI_HSYNC Sensor port horizontal sync CSI_PIXCLK Sensor port data latch clock LCD Controller LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for gate. driver (dedicated signal SPS for Sharp panel HR-TFT). LP/HSYNC Line Pulse or H Sync LSCLK Shift Clock ACD/OE Alternate Crystal Direction/Output Enable CONTRAST This signal is used to control the LCD bias voltage as contrast control. SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal). Table 3. Signal Names and Descriptions (Continued) Signal Name Function/Notes |
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