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MC68VZ328 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MC68VZ328 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 96 page MC9328MX1 Advance Information, Rev. 4 6 Freescale Semiconductor Signals and Connections 2 Signals and Connections Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Table 3. Signal Names and Descriptions Signal Name Function/Notes External Bus/Chip Select (EIM) A [24:0] Address bus signals D [31:0] Data bus signals EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24] EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16] EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8] EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0] OE Memory Output Enable—Active low output enables external data bus CS [5:0] Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. ECB Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. LBA Active low signal sent by flash device causing the external burst device to latch the starting burst address. BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. Bootstrap BOOT [3:0] System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles. SDIBA [3:0] SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash cycles. MA [11:10] SDRAM address signals MA [9:0] SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on SDRAM/SyncFlash cycles. |
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