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LT1715IMS Datasheet(PDF) 3 Page - Linear Technology |
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LT1715IMS Datasheet(HTML) 3 Page - Linear Technology |
3 / 16 page 3 LT1715 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ∆tPD Differential Propagation Delay (Note 13) Between Channels q 0.3 1 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tJITTER Output Timing Jitter VIN = 1.2VP-P (6dBm), ZIN = 50Ω tPD+ 15 psRMS f = 20MHz (Note 14) tPD – 11 psRMS ICC Positive Input Stage Supply Current + VS = VCC = 5V, VEE = – 5V q 12 mA (per Comparator) +VS = VCC = 3V, VEE = 0V q 0.9 1.6 mA IEE Negative Input Stage Supply Current + VS = VCC = 5V, VEE = – 5V q – 4.8 – 2.9 mA (per Comparator) +VS = VCC = 3V, VEE = 0V q – 3.8 – 2.4 mA IS Positive Output Stage Supply Current + VS = VCC = 5V, VEE = – 5V q 4.6 7.5 mA (per Comparator) VS = VCC = 3V, VEE = 0V q 3.7 6 mA The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1715C is guaranteed to meet specified performance from 0 °C to 70°C. The LT1715C is designed, characterized and expected to meet specified performance from –40 °C to 85°C but is not tested or QA sampled at these temperatures. The LT1715I is guaranteed to meet specified performance from –40 °C to 85°C. Note 3: Thermal resistances vary depending upon the amount of PC board metal attached to Pin 5 of the device. θJA is specified for a 2500mm2 3/32" FR-4 board covered with 2oz copper on both sides and with 100mm2 of copper attached to Pin 5. Thermal performance can be improved beyond the given specification by using a 4-layer board or by attaching more metal area to Pin 5. Note 4: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. Note 5: The LT1715 comparator includes internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of VTRIP+ and VTRIP–, while the hysteresis voltage is the difference of these two. Note 6: The common mode rejection ratio is measured with VCC = 5V, VEE = – 5V and is defined as the change in offset voltage measured from VCM = – 5.1V to VCM = 3.8V, divided by 8.9V. Note 7: The power supply rejection ratio is measured with VCM = 1V and is defined as the worst of: the change in offset voltage from VCC = + VS = 2.7V to VCC = + VS = 6V (with VEE = 0V) divided by 3.3V or the change in offset voltage from VEE = 0V to VEE = – 6V (with VCC = +VS = 6V) divided by 6V. Note 8: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring VOH and VOL with only 20mV of overdrive. Note 9: Maximum toggle rate is defined as the highest frequency at which a 100mV sinusoidal input results in an error free output toggling to greater than 4V when high and to less than 1V when low on a 5V output supply. Note 10: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP±. Note 11: tPD cannot be measured in automatic handling equipment with low values of overdrive. The LT1715 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that tPD limits can be guaranteed with this test. Note 12: Propagation Delay Skew is defined as: tSKEW = |tPDLH – tPDHL| Note 13: Differential propagation delay is defined as the larger of the two: ∆tPDLH = |tPDLHA – tPDLHB| ∆tPDHL = |tPDHLA – tPDHLB| Note 14: Package inductances combined with asynchronous activity on the other channel can increase the output jitter. See Channel Interactions in Applications Information. Specification above is with one channel active only. ELECTRICAL CHARACTERISTICS |
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