COP8ACC5 datasheet(30/41 Pages) NSC

Part #	COP8ACC5

Description	8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D

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Manufacturer	NSC [National Semiconductor (TI)]

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MICROWIRE/PLUS (Continued)

TABLE 9. MICROWIRE/PLUS Master Mode Clock Select

SL1

SL0

SK period

0

2Xt

C

0

1

4Xt

C

1

x

8Xt

C

Where t

C is the instruction cycle clock

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave.

Figure 18 shows how

two devices, microcontrollers and several peripherals may

be

interconnected

using

the

MICROWIRE/PLUS

arrangements.

WARNING

The SIO register should only be loaded when the SK clock is

low. Loading the SIO register while the SK clock is high will

result in undefined data in the SIO register. SK clock is nor-

mally low when not shifting.

Setting the BUSY flag when the input SK clock is high in the

MICROWIRE/PLUS slave mode may cause the current SK

clock for the SIO shift register to be narrow. For safety, the

BUSY flag should only be set when the input SK clock is low.

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register.

Table 10 summarizes the bit settings

required for Master mode of operation.

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bits in the Port G configuration regis-

ter. Table XI summarizes the settings required to enter the

Slave mode of operation.

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated.

TABLE 10. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

G4

G5

Operation

Config. Bit

Fun.

1

SO

Int.

MICROWIRE/PLUS

SK

Master

0

1

TRI-

Int.

MICROWIRE/PLUS

STATE

SK

Master

1

0

SO

Ext.

MICROWIRE/PLUS

SK

Slave

0

TRI-

Ext.

MICROWIRE/PLUS

STATE

SK

Slave

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK is normally low. In the normal mode

data is shifted in on the rising edge of the SK clock and the

data is shifted out on the falling edge of the SK clock. The

SIO register is shifted on each falling edge of the SK clock.

In the alternate SK phase operation, data is shifted in on the

falling edge of the SK clock and shifted out on the rising edge

of the SK clock.

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

DS012865-16

FIGURE 17. MICROWIRE/PLUS Block Diagram

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COP8ACC5 Datasheet(PDF) 30 Page - National Semiconductor (TI)

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