HY29F002TC-90 datasheet(6/38 Pages) HYNIX

Part #	HY29F002TC-90

Description	2 Megabit (256K x 8), 5 Volt-only, Flash Memory

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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6 / 38 page

6

Rev. 4.1/May 01

HY29F002T

Table 3. HY29F002T Bus Operations Requiring High Voltage 1, 2

Notes:

1. L = V

IL, H = VIH, X = Don’t Care.

See DC Characteristics for voltage levels.

2. Address bits not specified are Don’t Care.

3. See text for additional information.

4. SA = sector address. See Table 1.

n

o

i

t

a

r

e

p

O

3

#

E

C

#

E

O

#

E

W

#

T

E

S

E

R

]

3

1

:

7

1

[

A

]

9

[

A

]

6

[

A

]

1

[

A

]

0

[

A

]

0

:

7

[

Q

D

t

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P

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V

D

I

XH

A

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V

D

I

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X

t

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D

I

V

D

I

XH

X

V

D

I

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X

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S

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V

D

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X

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X

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d

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ML

L

H

X

V

D

I

LLL

D

A

x

0

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d

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C

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DL

L

H

X

V

D

I

LL

H

0

B

x

0

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S

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LL

H

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S 4

V

D

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LH

L

0

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1

0

x

0

The ‘Device Commands’ section of this document

provides details on the specific device commands

implemented in the HY29F002T.

Output Disable Operation

When the OE# input is at V

IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

Standby Operation

When the system is not reading from or writing to

the HY29F002T, it can place the device in the

Standby mode. In this mode, current consump-

tion is greatly reduced, and the data bus outputs

are placed in the high impedance state, indepen-

dent of the OE# input. The Standby mode can

invoked using two methods.

The device enters the CE# CMOS Standby mode

if the CE# and RESET# pins are both held at V

CC

± 0.5V. Note that this is a more restricted voltage

range than V

IH. If both CE# and RESET# are held

High, but not within V

CC ± 0.5V, the device will be

in the CE# TTL Standby mode, but the standby

current will be greater.

The device enters the RESET# CMOS Standby

mode when the RESET# pin is held at V

SS ± 0.5V.

If RESET# is held Low but not within V

SS ± 0.5V,

the HY29F002T will be in the RESET# TTL

Standby mode, but the standby current will be

greater. See Hardware Reset Operation section

for additional information on the reset operation.

The device requires standard access time (t

CE) for

read access when the device is in either of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

Hardware Reset Operation

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven Low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

the duration of the RESET# pulse. The device also

resets the internal state machine to reading array

data. If an operation was interrupted by the as-

sertion of RESET#, it should be reinitiated once

the device is ready to accept another command

sequence to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse as described in the Standby Operation sec-

tion above.

If RESET# is asserted during a program or erase

operation, the internal reset operation is completed

within a time of t

READY (during Automatic Algo-

rithms). The system can perform a read or write

operation after waiting for a minimum of t

READY or

until t

RH after the RESET# pin returns High, which-

ever is longer. If RESET# is asserted when a pro-

gram or erase operation is not executing, the re-

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