COP87L42CJ datasheet(9/28 Pages) NSC

Part #	COP87L42CJ

Description	8-Bit CMOS OTP Microcontrollers with 4k or 32k Memory and Comparator

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Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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Halt Mode

The device is a fully static device. The device enters the

HALT mode by writing a one to the G7 bit of the G data reg-

ister. Once in the HALT mode, the internal circuitry does not

receive any clock signal and is therefore frozen in the exact

state it was in when halted. In this mode the chip will only

draw leakage current.

The device supports three different methods of exiting the

HALT mode. The first method is with a low to high transition

on the CKO (G7) pin. This method precludes the use of the

crystal clock configuration (since CKO is a dedicated out-

put). It may be used either with an RC clock configuration or

an external clock configuration. The second method of exit-

ing the HALT mode is with the multi-Input Wakeup feature on

the L port. The third method of exiting the HALT mode is by

pulling the RESET input low.

If the two pin crystal/resonator oscillator is being used and

Multi-Input Wakeup causes the device to exit the HALT

mode, the WAKEUP signal does not allow the chip to start

running immediately since crystal oscillators have a delayed

start up time to reach full amplitude and freuqency stability.

The WATCHDOG timer (consisting of an 8-bit prescaler fol-

lowed by an 8-bit counter) is used to generate a fixed delay

of 256tc to ensure that the oscillator has indeed stabilized

before allowing instruction execution. In this case, upon de-

tecting a valid WAKEUP signal only the oscillator circuitry is

enabled. The WATCHDOG Counter and Prescaler are each

loaded with a value of FF Hex. The WATCHDOG prescaler is

clocked with the tc instruction cycle. (The tc clock is derived

by dividing the oscillator clock down by a factor of 10).

The Schmitt trigger following the CKI inverter on the chip en-

sures that the WATCHDOG timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specs. This Schmitt trigger is not part of the

oscillator closed loop. The start-up timeout from the WATCH-

DOG timer enables the clock signals to be routed to the rest

of the chip. The delay is not activated when the device

comes out of HALT mode through RESET pin. Also, if the

clock option is either RC or External clock, the delay is not

used, but the WATCHDOG Prescaler/-Counter contents are

changed. The Development System will not emulate the

256tc delay.

The RESET pin will cause the device to reset and start ex-

ecuting from address X’0000. A low to high transition on the

G7 pin (if single pin oscillator is used) or Multi-Input Wakeup

will cause the device to start executing from the address fol-

lowing the HALT instruction.

When RESET pin is used to exit the device from the HALT

mode and the two pin crystal/resonator (CKI/CKO) clock op-

tion is selected, the contents of the Accumulator and the

Timer T1 are undetermined following the reset. All other in-

formation except the WATCHDOG Prescaler/Counter con-

tents is retained until continuing. All information except the

WATCHDOG Prescaler/Counter contents is retained if the

device exits the HALT mode through G7 pin or Multi-Input

Wakeup.

G7 is the HALT-restart pin, but it can still be used as an input.

If the device is not halted, G7 can be used as a general pur-

pose input.

Note: To allow clock resynchronization, it is necessary to program two NOP’s

immediately after the device comes out of the HALT mode. The user

must program two NOP’s following the “enter HALT mode” (set G7

data bit) instruction.

MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous bidirectional

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with any of National Semi-

conductor’s MICROWIRE peripherals (i.e. A/D converters,

display drivers, EEPROMS, etc.) and with other microcon-

trollers which support the MICROWIRE/PLUS interface. It

consists of an 8-bit serial shift register (SIO) with serial data

input (SI), serial data output (SO) and serial shift clock (SK).

Figure 6 shows the block diagram of the MICROWIRE/PLUS

interface.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS in-

terface with the internal clock source is called the Master

mode of operation. Operating the MICROWIRE/PLUS inter-

face with an external shift clock is called the Slave mode of

operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,

the MSEL bit in the CNTRL register is set to one. The SK

clock rate is selected by the two bits, SL0 and SL1, in the

CNTRL register.

Table 3 details the different clock rates that

may be selected.

TABLE 3.

SL1

SL0

SK Cycle Time

00

2t

c

01

4t

c

1x

8t

c

where,

t

c is the instruction cycle time.

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS arrangement to start shifting the data. It

gets reset when eight data bits have been shifted. The user

may reset the BUSY bit by software to allow less than 8 bits

to shift. The device may enter the MICROWIRE/PLUS mode

either as a Master or as a Slave.

Figure 7 shows how two de-

vice microcontrollers and several peripherals may be inter-

connected using the MICROWIRE/PLUS arrangement.

Master MICROWIRE/PLUS Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally by the device. The

MICROWIRE/PLUS Master always initiates all data ex-

DS012529-7

FIGURE 6. MICROWIRE/PLUS Block Diagram

www.national.com

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