September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
7
Table 1: Device Family Key Features.........................................................................................................14
Table 2: Pin-out 8 Pin .................................................................................................................................15
Table 3: Pin-out 20 Pin ...............................................................................................................................15
Table 4: Pin-out 28 Pin ...............................................................................................................................16
Table 5: Pin-out 44 Pin ...............................................................................................................................16
Table 6: Pin-out 48 Pin ...............................................................................................................................17
Table 7: CPU Registers and Mnemonics ...................................................................................................19
Table 8: Flags Register ..............................................................................................................................20
Table 9: Accumulator Register (CPU_A)....................................................................................................20
Table 10: Index Register (CPU_X) .............................................................................................................21
Table 11: Stack Pointer Register (CPU_SP) ..............................................................................................21
Table 12: Program Counter Register (CPU_PC)........................................................................................21
Table 13: Source Immediate ......................................................................................................................21
Table 14: Source Direct..............................................................................................................................22
Table 15: Source Indexed ..........................................................................................................................22
Table 16: Destination Direct .......................................................................................................................22
Table 17: Destination Indexed....................................................................................................................23
Table 18: Destination Direct Immediate .....................................................................................................23
Table 19: Destination Indexed Immediate ..................................................................................................23
Table 20: Destination Direct Direct.............................................................................................................24
Table 21: Source Indirect Post Increment ..................................................................................................24
Table 22: Destination Indirect Post Increment............................................................................................24
Table 23: Instruction Set Summary (Sorted by Mnemonic)........................................................................25
Table 24: Flash Program Memory Map ......................................................................................................26
Table 25: RAM Data Memory Map .............................................................................................................26
Table 26: Bank 0 ........................................................................................................................................27
Table 27: Bank 1 ........................................................................................................................................28
Table 28: Port Data Registers ....................................................................................................................31
Table 29: Port Interrupt Enable Registers ..................................................................................................31
Table 30: Port Global Select Registers ......................................................................................................32
Table 31: Port Drive Mode 0 Registers ......................................................................................................32
Table 32: Port Drive Mode 1 Registers ......................................................................................................33
Table 33: Port Interrupt Control 0 Registers...............................................................................................33
Table 34: Port Interrupt Control 1 Registers...............................................................................................34
Table 35: Internal Main Oscillator Trim Register ........................................................................................35
Table 36: Internal Low Speed Oscillator Trim Register ..............................................................................36
Table 37: External Crystal Oscillator Trim Register....................................................................................37
Table 38: Typical Package Capacitances ..................................................................................................37
Table 39: System Clocking Signals and Definitions ...................................................................................38
Table 40: Oscillator Control 0 Register.......................................................................................................40
Table 41: Oscillator Control 1 Register.......................................................................................................40
Table 42: 24V1/24V2 Frequency Selection ................................................................................................41
Table 43: Interrupt Vector Table.................................................................................................................44
Table 44: General Interrupt Mask Register ................................................................................................45
Table 45: Digital PSoC Block Interrupt Mask Register ...............................................................................46
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