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AN7824 Datasheet(PDF) 6 Page - Fairchild Semiconductor |
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AN7824 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 / 17 page 6 5/22/97 AN7820/24 Table 5: Timing Specification Function Description Min Typ Max Unit tpd1 SPT7820/24, CLK to Data Valid Prop Delay - 14 18 nsec tdp2 MAX9686 Prop. Delay - 6 9 nsec tdp3 SPT7820/24, T(fall) Prop. Delay 4.5 7 10 nsec tdp4 74F174, Prop. Delay 4.5 7 10 nsec ts 74F174 Setup Time 4 - - nsec th 74174, Hold Time 4 - - nsec tpwH CLK Positive Pulse Width (SPT7820) 20 - 300 nsec tpwL CLK Negative Pulse Width (SPT7820) 20 - - nsec tpwH CLK Positive Pulse width (SPT7824) 10 - 300 nsec tpwL CLK Negative pulse Width (SPT7824) 10 - - nsec SPT7820/24 ACQUISITION TIME SPECIFICATION Figure 8: Acquisition Time Tacq 1 ANALOG INPUT CLOCK INPUT INTERNAL THA OUTPUT Settle to 1/2 LSB Vin Hold time (5 ns min) INTERNAL THA TIMING 50% HOLD TRACK TpwH Tacq 2 - 2V + 2V + FS - FS TRACK The acquisition time (Tacq) is defined as the hold to track full scale settling time for the internal track-and-hold (THA). Logic low of the clock input corresponds to track mode and logic high is the hold mode for the internal THA. Figure 8 shows two types of acquisition time: 1) Tacq 1 is the settling time of the THA when it is in track and it is driven by the analog input switching. 2) Tacq 2 is the amount of time it takes for the internal THA of the ADC to reacquire the analog input when switching from hold to track (CLK IN from high to low) to within 1/2 LSB. Both Tacq 1 and Tacq 2 need the same amount of time (see the acquisition time specification in the respective data sheet). The low-to-high clock transition should be placed after both the analog input and internal THA are settled. The analog input must remain for at least 5 ns (Vin hold time) after the low to high clock transition. Keep the clock positive pulse width (TpwH) to within the recommended limit. (Refer to the speci- fication in the respective data sheet.) TIMING CONSIDERATIONS WHEN USING AN EXTERNAL TRACK-AND-HOLD The signal-to-noise ratio (SNR) and the total harmonic distor- tion (THD) degrade as the analog input frequency increases. These parameters imply that the differential linearity error (DLE) and the integral linearity error (ILE) degrades as well at high frequency. This degradation is mainly due to aperture jitter and/or analog input bandwidth limitation and/or slew rate limitation of the SPT7820 and SPT7824. Below 1 MHz, the SNR and THD of the SPT7820 and SPT7824 are generally constant. In order to bring these accuracies up (at high frequency), you may need to buffer the analog input using a track-and-hold amplifier (THA). THAs can be imperfect (es- pecially at high frequency); otherwise, the dynamic perfor- mance of the SPT7820 or SPT7824 would be constant and equal to its performance at 1 MHz. Selecting an acceptable THA for a specific application is sometimes difficult. The timing diagram shown in figure 9 and table 6 illustrate the critical timing necessary when driving the ADC from a THA. Figure 9-Critical Timing Between External THA and ADC T R A C K H O L D th1 tacq (ADC) THA IN THA OUT THA DIFF CLK ADC CLK Droop Pedestal tHTS tTHS tpd1 Valid Data Valid Data tHTS ADC OUT Aperture delay (THA tacq ) |
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Similar Description - AN7824 |
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