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NCV7420 Datasheet(PDF) 11 Page - ON Semiconductor

Part # NCV7420
Description  LIN Transceiver with 3.3V or 5 V Voltage Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCV7420 Datasheet(HTML) 11 Page - ON Semiconductor

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NCV7420
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11
Table 8. DC CHARACTERISTICS – 5 V version
(VBB = 6 V to 26 V; TJ = −40°C to +150°C; Bus Load = 500 W (VBB to LIN); unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY − Pin VBB
IBB_ON
Supply current
Normal mode; LIN recessive
1.6
mA
IBB_STB
Supply current
Standby mode,
VBB = 6–18 V,
TJ < 105°C
70
mA
IBB_SLP
Supply current
Sleep mode, VBB = 6–18 V,
TJ < 105°C
20
mA
VOLTAGE REGULATOR − Pin VCC
VCC_OUT
Regulator output voltage
VCC load 1 mA − 30 mA
4.9
5.0
5.1
V
VCC load 0 mA − 50 mA
4.83
5.0
5.17
IOUT_MAX_ABS
Absolute maximum output current
Thermal shutdown must be
taken into account
50
mA
IOUT_LIM
Overcurrent limitation
50
100
170
mA
DVCC_OUT
Line Regulation (Note 28)
VBB 6−26 V, IOUT = 5 mA,
TJ = 25°C
0.9
mV
Load Regulation (Note 28)
IOUT 1−50 mA, VBB = 14 V,
TJ = 25°C
74
mV
VDO
Dropout Voltage (VBB−VCC_OUT)
Figure 19 (Notes 27, 28)
IOUT = 1 mA, TJ = 25°C
13
mV
IOUT = 10 mA, TJ = 25°C
136
mV
IOUT = 50 mA, TJ = 25°C
794
mV
LIN TRANSMITTER − Pin LIN
VLIN_dom_LoSup
LIN dominant output voltage
TxD = low; VBB = 7.3 V
1.2
V
VLIN_dom_HiSup
LIN dominant output voltage
TxD = low; VBB = 18 V
2.0
V
VLIN_rec
LIN Recessive Output Voltage (Note 23)
TxD = high; ILIN = 10 mA
VBB − 1.5
VBB
V
ILIN_lim
Short circuit current limitation
VLIN = VBB_MAX
40
200
mA
RSLAVE
Internal pull−up resistance
20
33
47
k
W
CLIN
Capacitance on pin LIN (Note 25)
15
25
pF
LIN RECEIVER − Pin LIN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vbus_dom
Bus voltage for dominant state
0.4
VBB
Vbus_rec
Bus voltage for recessive state
0.6
VBB
Vrec_dom
Receiver threshold
LIN bus recessive
→ dominant
0.4
0.6
VBB
Vrec_rec
Receiver threshold
LIN bus dominant
→ recessive
0.4
0.6
VBB
Vrec_cnt
Receiver center voltage
(Vrec_dom + Vrec_rec) / 2
0.475
0.525
VBB
Vrec_hys
Receiver hysteresis
(Vrec_rec − Vrec_dom)
0.05
0.175
VBB
ILIN_off_dom
LIN output current bus in dominant state
Driver off; VBB = 12 V;
VLIN = 0 V
−1
mA
ILIN_off_rec
LIN output current bus in recessive state
Driver off; VBB < 18 V
VBB < VLIN < 18 V
1
mA
23. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
24. By one of the trimming bits, following reconfiguration can be done during chip−level testing in order to fit the NCV7420−5 into different
interface: pins TxD and EN will have typ. 10 k
W pull−down resistor to ground and pin WAKE will have typ. 10 mA pull−up current source.
25. Guaranteed by design. Not tested.
26. VBB undervoltage threshold is always higher than VBB POR low level (VBB_UV_th > PORL_VBB)
27. Measured at output voltage VCC_OUT = (VCC_OUT@VBB = 6 V) – 2%.
28. Values based on design and characterization. Not tested in production.


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