S3C2510A datasheet(11/46 Pages) SAMSUNG

Part #	S3C2510A

Description	16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example

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Manufacturer	SAMSUNG [Samsung semiconductor]

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S3C2510A

PRODUCT OVERVIEW

1-11

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)

Group

Pin Name

Pin No.

I/O Type

Pad

Type

Description

System

Configurations

(21)

CLKMOD[1]

CLKMOD[0]

AB4

AC2

I

phic

The CLKMOD pin determines internal

clock scheme of S3C2510A. When

CLKMOD is “00”, the nfast clock mode is

defined. In this mode, the same clock is

used as CPU clock and system clock.

When CLKMOD is “01” or “10”, the sync

mode is defined. In this mode, the system

clock is half frequency of the CPU clock.

When CLKMOD is "11", the async clock

mode is defined. In this mode, the CPU

clock and system clock can operate

independently as long as the CPU clock is

faster than system clock.

In this case, BUS_FREQ[2:0] pins should

be 3b’000 to select PCI PLL, 3b’001 to

select USB PLL for programmable setting.

CPU_FREQ[2]

CPU_FREQ[1]

CPU_FREQ[0]

AE1

AD1

AC3

I

phic

CPU Clock Frequency Selection.

BUS_FREQ[2]

BUS_FREQ[1]

BUS_FREQ[0]

AD2

AB3

AC1

I

phic

System Bus Clock Frequency Selection.

nRESET

AB2

I

phis

Not Reset. NRESET is the global reset

input for the S3C2510A and nRESET must

be held to "low" for at least 64 clock cycles

for digital filtering.

TMODE

AF3

I

phicd

Test Mode. The TMODE pin setting is

interpreted as follows:

0 = normal operating mode

1 = chip test mode.

BIG

W3

I

phicd

BIG endian mode select pin.

When this pin is set to “0”, the S3C2510A

operates in litte endian mode. When this

pin is set to “1”, the S3C2510A operates in

big endian mode.

PCI_PCCDM

AA2

I

phic

PCI(1'b0) or PC Card(1'b1) Mode Select of

PCI & PC Card Controller

PCI_HOSTM

Y3

I

phic

Host (1'b1) or Agent (1'b0) Mode Select of

PCI & PC Card Controller

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