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CLC5623IN Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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CLC5623IN Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 12 page  9 http://www.national.com Figure 10: Transmission Line Matching Inverting gain applications: s Connect R3 directly to ground. s Make the resistors R4, R6, and R7 equal to Zo. s Make R5 II Rg = Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Power Dissipation Follow these steps to determine the power consumption of the CLC5623: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP and SOIC packages can dissipate at a given temperature is illustrated in Figure 11. The power derating curve for any CLC5623 package can be derived by utilizing the following equation: where Tamb = Ambient temperature (°C) θ JA = Thermal resistance, from junction to ambient, for a given package (°C/W Figure 11: Power Derating Curves Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5623 (CLC730075-DIP, CLC730074-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s Include 6.8 µF tantalum and 0.1µF ceramic capacitors on both supplies. s Place the 6.8 µF capacitors within 0.75 inches of the power pins. s Place the 0.1 µF capacitors less than 0.1 inches from the power pins. s Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. s Minimize all trace lengths to reduce series inductances. s Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730075/ CLC730074 evaluation boards. The evaluation board data sheet provides: s Evaluation board schematics s Evaluation board layouts s General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: s Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parame- ters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Ambient Temperature ( °C) 0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 180 IN IM 140 160 (175 Tamb JA °− ) θ + - R3 Z0 R6 Vo Z0 R1 R2 + - Rg Z0 R4 R5 V1 V2 +- Rf C6 R7 1/3 CLC5623 |
Similar Part No. - CLC5623IN |
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Similar Description - CLC5623IN |
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