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K4H511638M-TLA2 Datasheet(PDF) 9 Page - Samsung semiconductor |
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K4H511638M-TLA2 Datasheet(HTML) 9 Page - Samsung semiconductor |
9 / 53 page - 9 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock(CK) • Data I/O transactions on both edges of data strobe • Edge aligned data output, center aligned data input • LDM,UDM/DM for write masking only • Auto & Self refresh • 15.6us refresh interval(4K/64ms refresh) • Maximum burst refresh cycle : 8 • 66pin TSOP II package 1. Key Features 1.1 Features 1.2 Operating Frequencies *CL : Cas Latency Table 1. Operating frequency and DLL jitter - A2(DDR266A) - B0(DDR266B) - A0(DDR200) Speed @CL2 133MHz@CL2 100MHz 100MHz Speed @CL2.5 - 133MHz - DLL jitter ±0.75ns ±0.75ns ±0.8ns |
Similar Part No. - K4H511638M-TLA2 |
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Similar Description - K4H511638M-TLA2 |
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