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4X16E83VTW-6 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. 4X16E83VTW-6
Description  4 MEG x 16 EDO DRAM
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Maker  ETC [List of Unclassifed Manufacturers]
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Figure 3
OE# Control of DQs
V
V
IH
IL
CAS#
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
ROW
COLUMN (A)
COLUMN (B)
V
V
IH
IL
OE#
V
V
IOH
IOL
OPEN
DQ
tOD
VALID DATA (B)
VALID DATA (A)
COLUMN (C)
VALID DATA (A)
tOE
VALID DATA (C)
COLUMN (D)
VALID DATA (D)
tOD
tOEHC
tOD
tOEP
tOES
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
Figure 4
WE# Control of DQs
V
V
IH
IL
CAS#
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
ROW
COLUMN (A)
DON?T CARE
UNDEFINED
V
V
IH
IL
WE#
V
V
IOH
IOL
OPEN
DQ
tWPZ
The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
V
V
IH
IL
OE#
VALID DATA (B)
tWHZ
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
tWHZ
COLUMN (D)
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
4 MEG x 16
EDO DRAM




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