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16 Megabit FlashBank Memory

LE28DW1621T-80T (Draft3)

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SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan

R.1.20(4/27/2000) No.xxxx-2/20

The Auto Low Power Mode automatically puts the

LE28DW1621T in a near standby mode after data has been

active read current from typically 10mA to typically 5µA. The Auto

the range of 1mA/MHz of Read cycle time. If a concurrent

typically 40mA. The device exits the Auto Low Power mode with

any address transition or control signal transition used to initiate

another Read cycle, with no access time penalty.

Read

The Read operation of the LE28DW1621T Flash banks is

controlled by CE# and OE#, a chip enable and output enable

both have to be low for the system to obtain data from the

outputs. OE# is the output control and is used to gate data from

the output pins. The data bus is in high impedance state when

OE# is high. Refer to the timing waveforms for further details

(Figure 3).

When the read operation is executed without address change

after power switch on, CE# should be changed the level high

to low. If the read operation is executed after programing , CE#

should be changed the level high to low.

Write

All Write operations are initiated by first issuing the Software

Data Protect (SDP) entry sequence for Chip, Block, or Sector

Erase. Word Program in the selected Flash bank. Word

Program and all Erase commands have a fixed duration, that will

not vary over the life of the device, i.e., are independent of the

number of Erase/Program cycles endured.

Either Flash bank may be read to another Flash Bank during the

internally controlled write cycle.

The device is always in the Software Data Protected mode for

all Write operations Write operations are controlled by toggling

WE# or CE#. The falling edge of WE# or CE#, whichever occurs

last, latches the address. The rising edge of WE# or CE#,

whichever occurs first, latches the data and initiates the Erase

or Program cycle.

For the purposes of simplification, the following descriptions will

assume WE# is toggled to initiate an Erase or Program. Tog-

gling the applicable CE# will accomplish the same function.

(Note, there are separate timing diagrams to illustrate both WE#

and CE# controlled Program or Write commands.)

Word Program

The Word Program operation consists of issuing the SDP Word

Program command, initiated by forcing CE# and WE# low, and

OE# high. The words to be programmed must be in the erased

state, prior to programming. The Word Program command

programs the desired addresses word by word. During the

Word Program cycle, the addresses are latched by the falling

edge of WE#. The data is latched by the rising edge of WE#. (

See Figure 4-1 for WE# or 4-2 for CE# controlled Word Program

cycle timing waveforms, Table 3 for the command sequence,

and Figure 15 for a flowchart. )

During the Erase or Program operation, the only valid reads from

that bank are Data# Polling and Toggle Bit. The other bank may

be read.

The specified Chip, Block, or Sector Erase time is the only time

required to erase. There are no preprogramming or other com-

mands or cycles required either internally or externally to erase

the chip, block, or sector.

Erase Operations

The Chip Erase is initiated by a specific six-word load sequence

(See Tables 3). A Bank Erase will typically be less than 70 ms.

An alternative to the Chip Erase in the Flash bank is the Block or

Sector Erase. The Block Erase will erase an entire Block (32K

words) in typically 15 ms. The Sector Erase will erase an entire

sector (1024 words) in typically 15 ms. The Sector Erase

provides a means to alter a single sector using the Sector Erase

and Word Program modes. The Sector Erase is initiated by a

specific six-word load sequence (see Table 3).

During any Sector, Block, or Chip Erase within a bank, any other

bank may be read.

Chip Erase

The LE28DW1621T provides a Chip Erase mode, which allows

the user to clear the Flash bank to the "1"state. This is useful

when the entire Flash must be quickly erased.

The software Flash Chip Erase mode is initiated by issuing the

specific six-word loading sequence, as in the Software Data

Protection operation. After the loading cycle, the device enters

into an internally timed cycle. (See Table 3 for specific codes,

Figure 5-1 for a timing waveform, Figure12 for a flowchart. )

Block Erase

The LE28DW1621T provides a Block Erase mode, which allows

the user to clear any block in the Flash bank to the "1"state.

The software Block Erase mode is initiated by issuing the

specific six-word loading sequence, as in the Software Data

Protect operation. After the loading cycle, the device enters into

an internally timed Erase cycle. (See Table 3 for specific codes,

Figure 5-2 for the timing waveform, and Figure 13 for a flow-

chart.) During the Erase operation, the only valid reads are Data#

Polling and Toggle Bit from the selected bank, other banks may

perform normal read.

Sector Erase

The LE28DW1621T provides a Sector Erase mode, which

allows the user to clear any sector in the Flash bank to the "1"

state.

The software Sector Erase mode is initiated by issuing the