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CLC5523IN Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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CLC5523IN Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 12 page  http://www.national.com 8 Evaluation Boards Evaluation boards are available for both the 8-pin DIP and small outline package types. Evaluation kits that contain an evaluation board and CLC5523 samples can be obtained by calling National Semiconductor’s Customer Service Center at 1-800-272-9959. The 8-pin DIP evaluation kit part number is CLC730065. The 8-pin small outline evaluation kit part number is CLC730066. The DIP evaluation kit has been designed to utilize axial lead components. The small outline evaluation kit has been designed to utilize surface mount components. The circuit diagram shown in Figure 5, applies to both the DIP and the small outline evaluation boards. Gain Control RX 50 W Vin Rg GND VG I- Vo -VCC +VCC Rin 50 W Input Signal Rg 100 W 0.1 mF 6.8 mF Rf 1k Wž Ro 50 Wž 0.1 mF 6.8 mF -5V 5V Output X1 * 25 W * 25 W series resistor is not required on the small outline device and does not appear on the small outline board Figure 5: Evaluation Board Schematic Printed Circuit Board Layout High frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most impor- tant layout points to follow are: s Use a ground plane s Bypass each power supply pin with these capacitors: s a high-quality 0.1 mF ceramic capacitor placed less than 0.2” (5mm) from the pin s a 6.8 mF tantalum capacitor less than 2” (50mm) from the pin s for the plastic DIP package, a high-quality 1000pF ceramic capacitor placed less than 0.1” (3mm) from the pin Capacitively bypassing power pins to a good ground plane with a minimum of trace length (inductance) is necessary for any high speed device, but it is particularly important for the CLC5523. s Establish wide, low impedance, power supply traces s For the plastic DIP package, a 25 W resistor should be connected from pin 4 to ground with a minimum length trace s Minimize or eliminate sources of capacitance between the Rf pin and the output pin. Avoid adjacent feedthrough vias between the Rf and output leads since such a geometry may give rise to a significant source of capacitance. s Minimize trace and lead lengths for components between the inverting and output pins s Remove ground plane 0.1” (3mm) from all input/output pads s For prototyping, use flush-mount printed circuit board pins; never use high profile DIP sockets To minimize high frequency distortion, other layout issues need be addressed: s Short, equal length, low impedance power supply return paths from the load to the supplies s avoid returning output ground currents near the input stage. |
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