5

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+5.0V

-5.2V

differential voltage between any two GND’s

10mV

analog input voltage range

±2V

0V to +5.0V

0V to -2.0V

5pF to 100pF

thermal data

θ

θ

16-pin plastic

50

60

16-pin Cerdip

20

65

16-pin SOIC

60

75

20-terminal LCC

20

35

16-pin side brazed

20

50

-0.5V to +7.0V

+0.5V to -7.0V

differential voltage between any two GND’s

200mV

analog input voltage range

digital input voltage range

output short circuit duration (shorted to GND)

Infinite

junction temperature

+150°C

operating temperature range

CLC533AJP/AJE/AIB

-40°C to +85°C

storage temperature range

-65°C to +150°C

lead solder duration (+300°C)

10 sec

ESD rating (human body model)

<500V

Recommended Operating Conditions

Note 1: Test levels are as follows:

*

AJ : 100% tested at +25°C.

Note 2: Settling time measured from the 50% analog output

transition.

Note 3: Absolute maximum ratings are limiting values, to be

applied individually, and beyond which the serviceability of the cir-

cuit may be impaired. Functional operability under any of these

conditions is not necessarily implied. Exposure to maximum rat-

ings for extended periods may affect device reliability.

System Timing Diagram

Switching Transient Timing Diagram

APPLICATIONS INFORMATION

Operation

The CLC533 is a 4:1 analog multiplexer designed with a

closed loop architecture to provide very low harmonic

distortion and superior channel to channel isolation. This

low

distortion,

coupled

with

very

fast

switching

speed make the CLC533 an ideal multiplexer for data

conversion applications.

User selectable ECL or TTL

select logic adds to the versatility of this device. External

frequency

response

compensation

allows

the

performance of the CLC533 to be optimized for each

application.

Digital Interface and Channel Select

The CLC533 has two channel select pins which can be

used to select any one of the four inputs.

These

digital inputs can be configured to meet TTL, ECL or

ECL 10K switching levels (Figure 1). For TTL or CMOS

internal series resistor which makes it possible to

according to the truth table shown on the front page. A

more positive voltage is considered to be a logic ‘1’.

up resistors will select the D input to be passed through

to the output.

Compensation

The CLC533 is externally compensated, allowing

the user to select the bandwidth that best suits

the application. Decreasing bandwidth has two

advantages: lower noise and lower switching tran-

sients. In a sampled system, noise at frequencies

Package Thermal Resistance

Package

θ

JC

θ

JA

AJP

45°C/W

95°C/W

AJE

35°C/W

100°C/W

CERDIP

25°C/W

65°C/W

Reliability Information

Transistor count

144