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HM628128DLTS-7SL Datasheet(PDF) 7 Page - Hitachi Semiconductor |
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HM628128DLTS-7SL Datasheet(HTML) 7 Page - Hitachi Semiconductor |
7 / 20 page HM628128D Series 7 AC Characteristics (Ta = –20 to +70 °C, V CC = 5.0 V ± 10%, unless otherwise noted.) Test Conditions • Input pulse levels: V IL = 0.8 V, VIH = 2.4 V • Input rise and fall time: 5 ns • Input timing reference levels: 1.5 V • Output timing reference level: 1.5 V • Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7) 1 TTL Gate+ CL (50 pF) (HM628128D-5) (Including scope and jig) Read Cycle HM628128D -5 -7 Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 55 — 70 — ns Address access time t AA — 55 — 70 ns Chip select access time t ACS1 — 55 — 70 ns t ACS2 — 55 — 70 ns Output enable to output valid t OE — 30 — 35 ns Output hold from address change t OH 10 — 10 — ns Chip selection to output in low-Z t CLZ1 10 — 10 — ns 2, 3 t CLZ2 10 — 10 — ns 2, 3 Output enable to output in low-Z t OLZ 5 — 5 — ns 2, 3 Chip deselection to output in high-Z t CHZ1 0 20 0 25 ns 1, 2, 3 t CHZ2 0 20 0 25 ns 1, 2, 3 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1, 2, 3 |
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