HM628128D Series

8

Write Cycle

HM628128D

-5

-7

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

70

—

ns

Address valid to end of write

t

AW

50

—

60

—

ns

Chip selection to end of write

t

CW

50

—

60

—

ns

5

Write pulse width

t

WP

40

—

50

—

ns

4, 13

Address setup time

t

AS

0—

0—

ns

6

Write recovery time

t

WR

0—

0—

ns

7

Data to write time overlap

t

DW

20

—

25

—

ns

Data hold from write time

t

DH

0—

0—

ns

Output active from output in high-Z

t

OW

5—

5—

ns

2

Output disable to output in high-Z

t

OHZ

0

20

0

25

ns

1, 2, 8

WE to output in high-Z

t

WHZ

0

20

0

25

ns

1, 2, 8

Notes: 1. t

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. At any given temperature and voltage condition, t

device and from device to device.

4. A write occurs during the overlap (t

A write begins

at the later transition of

CS1 going low, CS2 going high, or WE going low. A write ends at the

earlier transition of

CS1 going high, CS2 going low, or WE going high. t

beginning of write to the end of write.

5. t

6. t

7. t

cycle.

8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite

phase to the outputs must not be applied.

9. If the

CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low,

the output remain in a high impedance state.

10. Dout is the same phase of the write data of this write cycle.

11. Dout is the read data of next address.

12. If

CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the

input signals of the opposite phase to the outputs must not be applied to them.

13. In the write cycle with

OE low fixed, t

data bus contention. t