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CLC522ALC Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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CLC522ALC Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 8 page  Component parasitics also influence high frequency results, therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. If socketing is necessary, it is recom- mended to use low impedance flush mount connector jacks such as Cambion (P/N 450-2598). Application Circuits Four-Quadrant Multiplier Applications requiring multiplication, squaring or other non-linear functions can be implemented with four-quad- rant multipliers. The CLC522 implements a four-quad- rant multiplier as illustrated in figure 8. Frequency Shaping Frequency shaping and bandwidth extension of the CLC522 can be accomplished using parallel networks connected across the Rg ports. The network shown in the Fig. 9 schematic will effectively extend the CLC522's bandwidth. 2nd Order Tuneable Bandpass Filter The CLC522 Variable-Gain Amplifier placed into feed- back loops provide signal processing functions such as 2nd order tuneable bandpass filters. The center fre- quency of the 2nd order bandpass illustrated on the front page is adjusted through the use of the CLC522's gain- control voltage, Vg. The integrators implemented with two CLC420s, provide the coefficients for the transfer function. Input Referred Voltage Noise vs AVmax 0 10 20 3040 50 6070 80 90 100 Maximum Gain Setting, AVmax (V/V) 100 10 1 Circuit Layout Considerations Please refer to the CLC522 Evaluation Board Literature for precise layout guidelines. Good high-frequency op- eration requires all of the de-coupling capcitors shown in Fig. 6 to be placed as close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate ground plane and low- inductive power returns are also required of the layout. Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9, 10 and 12 as shown in Fig. 7 will assure best high frequency performance. Vref (pin 9) to ground should include a small resistor value of 25 ohms or greater to buffer the internal voltage follower. The parasitic induc- tance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or circuit oscillation. This should be treated with a small series resistor between output (pin 10) and CL (see the plot “Settling Time vs. Capacitive Load" for a recom- mended series resistance). Fig. 5 Fig. 6 Fig. 7 Rf Rg RT 50 Ω 50 Ω 50 Ω Vbaseband Vout Vcarrier 25 Ω 10 12 3 4 2 9 5 6 CLC522 Rm = 2Rg 1.85 R1 = RT || Rm || Rs R1 Rs RT = RmRs Rm-Rs Fig. 8 Fig. 9 http://www.national.com 6 |
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