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CY7C132/CY7C136
CY7C142/CY7C146
8
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)[15, 23]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)[15, 24]
Notes:
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
CE
R/W
ADDRESS
OE
DOUT
DATAIN
C132-10
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
CE
R/W
ADDRESS
DOUT
DATAIN
tLZWE
DATA VALID
C132-11
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