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CLC449AJE Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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CLC449AJE Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 12 page 7 http://www.national.com A 2-Tone, 3rd Order IMD Intercept plot is found in the Typical Performance Characteristics section. The output power level is taken at the load. Third-order harmonic distortion is calculated with the formula: HD3rd = 2 • (IP3o – Po) where: • IP3o = third-order output intercept, dBm at the load. • Po = output power level, dBm at the load. • HD3rd = third-order distortion from the fundamental, -dBc. • dBm is the power in mW, at the load, expressed in dB. Realized third-order output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that improve 3rd order distortion are: • short and equal return paths from the load to the supplies. • de-coupling capacitors of the correct value. • higher load resistance. • a lower ratio of the output swing to the power supply voltage. Dynamic Range (Noise) In RF applications, noise is frequently specified as Noise Figure (NF). Figure 7 plots NF for the CLC449 at a gain of 10, with a feedback resistor Rf of 100Ω, and with no input matching resistor. The minimum Noise Figure (2.5dB) for these conditions occurs when the source resistance equals 700 Ω. Figure 7. Noise Figure Plot Figure 8: CLC449 Noise Model The CLC449 noise model in Figure 8 is used to develop the equation below. The equation for Noise Figure (NF) is: where: • Rs is the source resistance at the non- inverting input. • There is no matching resistor from the input to ground. • eni, ibn, ibi are the voltage and current noise density terms (see in the Distortion and Noise Response sub-section of the Electrical Characteristics section). • 4kT = 16 x 10-21J, T = 290°K. • Rf is the feedback resistor and Rg is the gain setting resistor. Printed Circuit Board Layout and Measurement High Frequency op amp performance is strongly depen- dent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: • Use a ground plane. • Bypass power supply pins with monolithic capacitors of about 0.1 µF value and place the capacitors less than 0.1” (3mm) from the pin. • Bypass power supply pins with 6.8µF tantalum capacitors for large signal current swings or improved power supply noise rejection. • Minimize trace and lead lengths for components between the inverting and output pins. • Remove ground plane underneath the amplifier package and within 0.1” (3mm) of all input/output pads. • If parts must be socketed, always use flush-mount socket pins instead of high profile sockets. Evaluation boards are available for proto-typing and mea- surements. Additional layout information is available in the evaluation board literature. + - CLC449 en Vo Rs ibn + - Vs Rf Rg * * ibi * NF 10LOG e i R 4 TR i R ||R 4 T R ||R 4TR ni bn s 2 s bi f g 2 f g s 2 = + () ++ ⋅ () +⋅ kk k Source Resistance ( Ω) 20 15 0 10 100 10000 10 5 1000 |
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