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CLC412AJE Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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CLC412AJE Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 12 page bandwidth curves, labeled "BW", correspond to the two (solid) "Rf" curves. These results may deviate from that produced by the analysis of OA-13 since these plots were produced from an actual board layout that included parasitic capacitances not accounted for by the analysis of OA-13. It should be noted that a non-inverting gain of +1V/V requires an Rf =1k Ω and the output voltage used for both plots is 2Vpp. In order to bandlimit the CLC412 at any particular gain setting, a larger value of Rf (than previously recommended in the plots above) is needed. Following the analysis in OA-13, we find the CLC412’s "optimum feedback transimpedance", Z t*, below. The "optimum feedback transimpedance" is unique for each current-feedback op amp and determines the recommended value of Rf for a particular gain setting. Drawing a horizontal line on the “Open-loop Transimpedance, Z(s)” plot from 57.5dB (on the left vertical axis), we find the intersection with the transimpedance magnitude trace occurs at a frequency of 180MHz. This frequency is only an approximation of the CLC412’s small-signal bandwidth. From this intersection, one can see that an increase in Z t will produce a new intersection occurring at a lower frequency. This is the process to follow when bandlimiting. Once the target small-signal bandwidth is determined, the new value of Zt is picked off the graph at the point where the this frequency and the transimpedance magnitude trace intersect. One can then back track to figure the value of the feedback resistor, Rf=Z t-Rin(1+Rf/Rg). This new value of Rf will produce the desired frequency roll-off. Circuit Layout With all high-frequency devices, board layouts with stray capacitances have a strong influence over AC performance. The CLC412 is no exception and its input and output pins are particularly sensitive to the coupling of parasitic capacitances (to ac ground) arising from traces or pads placed too closely (<0.1") to power or ground planes. In some cases, due to the frequency response peaking caused by these parasitics, a small adjustment of the feedback resistor value will serve to compensate the frequency response. Also, it is very important to keep the parasitic capacitance across the feedback resistor to an absolute minimum. The performance plots in the data sheet can be reproduced using the evaluation boards available from Comlinear. There are two types of boards; the DIP (#730038) and SOIC (#730036). The #730036 board uses all SMT parts for the evaluation of the CLC412 in its surface mount package. Either of these layouts can assist the designer in obtaining the desired performance. In addition, the boards can serve as an example layout for the final production printed circuit board. Care must also be taken with the CLC412's layout in order to achieve the best circuit performance, particularly channel-to-channel isolation. The decoupling capacitors (both tantalum and ceramic) must be chosen with good high frequency characteristics to decouple the power supplies and the physical placement of the CLC412’s external components is critical. Grouping each amplifier’s external components with their own ground connection and separating them from the external components of the opposing channel with the maximum possible distance is recommended. The input (Rin) and gain-setting resistors (Rg) are the most critical. It is also recommended that the ceramic decoupling capacitor (0.1 µFchiporradial-leaded with low ESR) should be placed as closely to the power pins as possible. Package Parasitics In addition to the parasitic capacitances arising from the board layout, each of the CLC412's packages has its own characteristic set of parasitic capacitances and inductances causing frequency response variation from package to package as shown in the plot below labeled "Frequency Response vs. Package Type". Due to its much smaller size, the CLC412AJE (8-pin SOIC) shows the least amount of peaking. Matching Performance With proper board layout, the AC performance match between the two CLC412’s amplifiers can be tightly ZR R R R LOG dB t f in f g ∗ =+ + =+ + = () = 1 634 60 1 634 634 754 20 754 57 5 Ω . ½CLC412 ½CLC412 Vin Vout 634 Ω 314 Ω 634 Ω 25 Ω 59 Ω 50 Ω 50 Ω 50 Ω 50 Ω 634 Ω + + - - Figure 3 http://www.national.com 6 |
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