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APPLICATION INFORMATION

TPS793xx

GND

EN

NR

IN

OUT

V

IN

V

OUT

0.1

µF

0.01

µF

2.2

µF

External Capacitor Requirements

Board Layout Recommendation to Improve PSRR and Noise Performance

TPS79301, TPS79318

TPS79325, TPS79328, TPS793285

TPS79330, TPS79333, TPS793475

SLVS348H – JULY 2001 – REVISED OCTOBER 2004

The TPS793xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive

battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output

noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA

when the regulator is turned off.

A typical application circuit is shown in Figure 22.

Figure 22. Typical Application Circuit

A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the

TPS793xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A

higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device

is located several inches from the power source.

Like most low dropout regulators, the TPS793xx requires an output capacitor connected between OUT and GND

to stabilize the internal control loop. The minimum recommended capacitance is 2.2 µF. Any 2.2-µF or larger

ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load

current is not expected to exceed 100 mA, a 1.0-µF ceramic capacitor can be used.

The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx has an NR pin which

is connected to the voltage reference through a 250-k

Ω internal resistor. The 250-kΩ internal resistor, in

conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the

voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate

properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR

drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have

minimal leakage current. The bypass capacitor should be no more than 0.1-µF to ensure that it is fully charged

during the quickstart time provided by the internal switch shown in the Functional Block Diagrams

capacitor and a 2.2-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance

increases due to the RC time constant at the NR pin that is created by the internal 250-k

Ω resistor and external

capacitor.

To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board

pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND

pin of the device.

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