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P82B96T Datasheet(PDF) 8 Page - NXP Semiconductors |
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P82B96T Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 16 page Philips Semiconductors Product data P82B96 Dual bi-directional bus buffer 2004 Mar 26 8 frequency will be lower than calculated from the programmed clock periods. In the example for 25 meters the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising edge is delayed 570 ns. The required additional LOW period is (490 + 570) = 1060 ns and the I2C-bus specifications already include an allowance for a worst case bus risetime 0 to 70% of 425 ns. (The bus risetime can be 300 ns 30% to 70%, which means it can be 425 ns 0–70%. The 25-meter cable delay times as quoted already include all rise/fall times.) Therefore, the micro only needs to be programmed with an addtional (1060 – 400 – 425) = 235 ns, making a total programmed LOW period 1535 ns. The programmed LOW will the be stretched by 400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH period of 600 ns, yields a cycle period of 2535 ns or 394 kHz. Note that in both the 100-meter and 250-meter examples the capacitive loading on the I2C-buses at each end is within the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a ‘hybrid’ mode because it relies on the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large propagation delays so these systems need to operate well below the 400 kHz limit but illustrate how they can still exceed the 100 kHz limit provided all parts are capable of Fast mode operation. The fastest example illustrates how the 400 kHz limit can be exceeded provided master and slave parts have delay specifications smaller than the maximum allowed. Many Philips slaves have delays shorter than 600 ns, but none have that guaranteed. SCL SDA su01786 P82B96 VCC I2C MASTER GND SX SY RX TX RY TY VCC1 VCC2 SCL SDA P82B96 VCC I2C SLAVE(S) GND SX SY RX TX RY TY R1 R1 R2 R2 C2 C2 BAT54A BAT54A C2 C2 R2 R2 R1 R1 CABLE PROPAGATION DELAY ' 5 ns/m +V CABLE DRIVE Figure 5. Driving ribbon or flat telephone cables EXAMPLES OF BUS CAPABILITY (refer to Figure 5) +VCC +V +VCC R1 R2 C2 CABLE CABLE CABLE SET MASTER NOMINAL SCL EFFECTIVE BUS MAXIMUM SLAVE +VCC1 CABLE +VCC2 R1 R2 (pF) LENGTH CAPACITANCE DELAY HIGH PERIOD LOW PERIOD CLOCK SPEED RESPONSE DELAY 5 V 12 V 5 V 750 2.2 k 400 250 m Not applicable (delay based) 1.25 µs 600 ns 4000 ns 120 kHz Normal spec. 400 kHz parts 5 V 12 V 5 V 750 2.2 k 220 100 m Not applicable (delay based) 500 ns 600 ns 2600 ns 185 kHz Normal spec. 400 kHz parts 3.3 V 5 V 3.3 V 330 1 k 220 25 m 1 nF 125 ns 600 ns 1500 ns 390 kHz Normal spec. 400 kHz parts 3.3 V 5 V 3.3 V 330 1 k 100 3 m 120 pF 15 ns 600 ns 1000 ns 500 kHz 600 ns |
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