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GAL20RA10B-30LP Datasheet(PDF) 7 Page - Lattice Semiconductor

Part # GAL20RA10B-30LP
Description  High-Speed Asynchronous E2CMOS PLD Generic Array Logic?
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

GAL20RA10B-30LP Datasheet(HTML) 7 Page - Lattice Semiconductor

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Specifications GAL20RA10B
7
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC = 5.0V, VI = 2.0V
C
I/O
I/O Capacitance
10
pF
V
CC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
tpd
A
Input or I/O to Combinatorial Output
2
7.5
2
10
15
20
30
ns
tco
A
Clock to Output Delay
2
9
2
11
15
20
30
ns
tsu
Setup Time, Input or Fdbk before Clk
3
4
7
10
20
ns
th
Hold Time, Input or Fdbk after Clk
2
3
3
3
10
ns
fmax3
A
Maximum Clock Frequency with
83.3
66.7
45.0
33.3
20.0
MHz
External Feedback, 1/(tsu + tco)
A
Maximum Clock Frequency with
83.3
71.4
50.0
41.7
25.0
MHz
No Feedback
twh
Clock Pulse Duration, High
6
7
10
12
20
ns
twl
Clock Pulse Duration, Low
6
7
10
12
20
ns
ten/tdis
B,C
I or I/O to Output Enabled / Disabled
7.5
10
15
20
30
ns
ten/tdis
B,C
OE to Output Enabled / Disabled
5
9
12
15
20
ns
tar/tap
A
Input or I/O to Async. Reset / Preset
9
11
15
20
30
ns
tarw/tapw
Async. Reset / Preset Pulse Duration
6
10
15
20
20
ns
tarr/tapr
Async. Reset / Preset Recovery Time
7
7
10
12
20
ns
twp
Preload Pulse Duration
8
10
15
20
30
ns
tsp
Preload Setup Time
5
7
10
15
25
ns
thp
Preload Hold Time
5
7
10
15
25
ns
UNITS
-30
MIN.
MAX.
-20
MIN.
MAX.
-15
MIN.
MAX.
-10
MIN.
MAX.
PARAM.
DESCRIPTION
TEST
COND1.
-7
MIN.
MAX.
COM
COM
COM
COM / IND
COM
1) Refer to Switching Test Conditions section.
2) Refer to fmax Descriptions section.
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A = 25°C, f = 1.0 MHz)


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