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CLC021 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. CLC021
Description  SMPTE 259M Digital Video Serializer with EDH Generation and Insertion
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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 5 page
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DC Electrical Characteristics—CLC021AVGZ-3.3 (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
V
OH
CMOS Output Voltage
High Level
I
OH =−8 mA
All CMOS
Outputs
2.4
3.0
V
DD
V
V
OL
CMOS Output Voltage
Low Level
I
OL =+8 mA
0.0
0.3
V
SS + 0.5V
V
V
SDO
Serial Driver Output
Voltage
R
L =75
Ω 1%,
R
REF = 1.69 k
Ω 1%,
Figure 2
SDO, SDO
720
800
880
mV
P-P
I
DD
Power Supply Current,
Total
R
L =75
Ω 1%,
R
REF = 1.69 k
Ω 1%,
P
CLK = 27 MHz, NTSC
Colour Bar Pattern,
Figure 2
33
55
mA
AC Electrical Characteristics—CLC021AVGZ-5.0
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
BR
SDO
Serial Data Rate
(Note 5)
SDO, SDO
100
400
Mbps
F
PCLK
Reference Clock
Input Frequency
P
CLK
10
40
MHz
Reference Clock Duty
Cycle
P
CLK
45
50
55
%
t
r,tf
Rise Time, Fall Time
D
N,PCLK
1.0
1.5
3.0
ns
t
j
Serial Output Jitter
270 Mbps,Figure 2, (Note 6)
SDO, SDO
220
ps
P-P
t
jit
Serial Output Jitter
(Notes 4, 5)
100
200
ps
P-P
t
r,tf
Rise Time, Fall Time
20%–80%, (Notes 4, 5)
500
800
1500
ps
Output Overshoot
(Note 4)
1
%
t
LOCK
Lock Time
(Notes 5, 7)
75
µs
t
SU
Setup Time
Figure 3 (Note 4)
D
N to PCLK
32
ns
t
HLD
Hold Time
Figure 3 (Note 4)
D
N from PCLK
32
ns
L
GEN
Output Inductance
(Note 4)
SDO, SDO
6nH
R
GEN
Output Resistance
(Note 4)
25k
AC Electrical Characteristics—CLC021AVGZ-3.3
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
BR
SDO
Serial Data Rate
(Note 5)
SDO, SDO
100
400
Mbps
F
PCLK
Reference Clock
Input Frequency
P
CLK
10
40
MHz
Reference Clock Duty
Cycle
P
CLK
45
50
55
%
t
r,tf
Rise Time, Fall Time
D
N,PCLK
1.0
1.5
3.0
ns
t
j
Serial Output Jitter
270 Mbps,Figure 2, (Note 6)
SDO, SDO
220
ps
P-P
t
jit
Serial Output Jitter
(Notes 4, 5)
100
200
ps
P-P
t
r,tf
Rise Time, Fall Time
20%–80%, (Notes 4, 5)
500
800
1500
ps
Output Overshoot
(Note 4)
1
%
t
LOCK
Lock Time
(Notes 5, 7)
75
µs
t
SU
Setup Time
Figure 3 (Note 4)
D
N to PCLK
42
ns
t
HLD
Hold Time
Figure 3 (Note 4)
D
N from PCLK
42
ns
www.national.com
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