ADuM131D0BRZ datasheet(4/22 Pages) AD

Part #	ADuM131D0BRZ

Description	3.0 kV RMS/3.75 kV RMS Triple-Channel Digital Isolators

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ADuM130D/ADuM130E/ADuM131D/ADuM131E

Data Sheet

Rev. A | Page 4 of 22

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

AC SPECIFICATIONS

Output Rise/Fall Time

tR/tF

2.5

ns

10% to 90%

Common-Mode Transient

Immunity7

|CMH|

75

100

kV/µs

VIx = VDDx, VCM = 1000 V,

transient magnitude = 800 V

|CML|

75

100

kV/µs

VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

1

150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.

2

IOx is the Channel x output current, where x = A, B, or C.

3

VIxH is the input side logic high.

4

VIxL is the input side logic low.

5

VI is the voltage input.

6

E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers

to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-

mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode

voltage edges.

Table 2. Total Supply Current vs. Data Throughput

1 Mbps

25 Mbps

100 Mbps

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

SUPPLY CURRENT

ADuM130D/ADuM130E

Supply Current Side 1

IDD1

5.6

9.0

6.3

9.8

9.4

14.3

mA

Supply Current Side 2

IDD2

1.9

3.7

3.1

4.9

6.8

10

mA

ADuM131D/ADuM131E

Supply Current Side 1

IDD1

4.6

7.2

5.5

8.3

8.8

11.9

mA

Supply Current Side 2

IDD2

3.6

5.8

4.6

6.8

8.0

11.3

mA

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended

operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications

are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

PW

6.6

ns

Within PWD limit

Data Rate1

150

Mbps

Within PWD limit

Propagation Delay

tPHL, tPLH

4.8

6.8

14

ns

50% input to 50% output

Pulse Width Distortion

PWD

0.7

3

ns

|tPLH − tPHL|

Change vs. Temperature

1.5

ps/°C

Propagation Delay Skew

tPSK

7.5

ns

Between any two devices at the

same temperature, voltage, and

load

Channel Matching

Codirectional

tPSKCD

0.7

3.0

ns

Opposing Direction

tPSKOD

0.7

3.0

ns

Jitter

640

ps p-p

See the Jitter Measurement section

75

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold

Logic High

VIH

0.7 × VDDx

V

Logic Low

VIL

0.3 × VDDx

V

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