PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

Pericom Semiconductor Corporation  

3 

www.pericom.com     

 

6.1.19

 

RESERVED REGISTER – OFFSET 52H-56H ..........................................................................................................24

 

6.1.20

 

HBLEN REGISTER – OFFSET 57H/58H/59H/5AH(Default=90H) ....................................................................24

 

6.1.21

 

RESERVED REGISTER – OFFSET 5BH...................................................................................................................24

 

6.1.22

 

BGCTL-REGISTER – OFFSET 5CH(Default=00H) ...............................................................................................24

 

6.1.23

 

RESERVED REGISTER – OFFSET 5DH-5FH.........................................................................................................24

 

6.1.24

 

RESERVED REGISTER – OFFSET 60H ...................................................................................................................24

 

6.1.25

 

CRYSTAL CLOCK SELECT REGISTER – OFFSET 61H(Default=03H) ............................................................24

 

6.1.26

 

36M/GPIO_OE REGISTER – OFFSET 62H(Default=00H)...................................................................................24

 

6.1.27

 

CHANNEL ID01 REGISTER – OFFSET 63H(Default=10H)................................................................................25

 

6.1.28

 

CHANNEL ID23 REGISTER – OFFSET 64H(Default=32H)................................................................................25

 

6.1.29

 

PIXEL OUTPUT BUS TRI-STATE CONTROL REGISTER – OFFSET 65H(Default=00H) ...........................25

 

6.1.30

 

RESERVED REGISTER – OFFSET 66-6FH .............................................................................................................26

 

6.1.31

 

AUDIO CLOCK CONTROL REGISTER – OFFSET 70H(Default=08H) ...........................................................26

 

6.1.32

 

I2S AUDIO INPUT CONTROL REGISTER – OFFSET 71H(Default=00H)......................................................26

 

6.1.33

 

RESERVED REGISTER – OFFSET72H-7AH ..........................................................................................................26

 

6.1.34

 

SDOUT_M SELECT (R) REGISTER – OFFSET 7BH(Default=00H)...................................................................26

 

6.1.35

 

SDOUT_M SELECT (L) REGISTER – OFFSET 7CH(Default=00H)...................................................................27

 

6.1.36

 

EXTENDED LINE SELECT REGISTER – OFFSET 7DH(Default=E4H)............................................................27

 

6.1.37

 

SDOUT_M REGISTER– OFFSET 7EH(Default=00H) .........................................................................................28

 

6.1.38

 

MIX RATIO VALUE FOR LINE_IN4 REGISTER – OFFSET 7FH(Default=08H)............................................28

 

6.1.39

 

SOFTWARE RESET REGISTER– OFFSET 80H(Default=00H) ...........................................................................29

 

6.1.40

 

RESERVED REGISTER – OFFSET 81H-84H ..........................................................................................................29

 

6.1.41

 

VIDEO SOURCE SELECTION REGISTER – OFFSET 85H (Default=00H) ......................................................29

 

6.1.42

 

RESERVED REGISTER – OFFSET 86H-88H ..........................................................................................................29

 

6.1.43

 

AUDIO FS MODE REGISTER– OFFSET 89H(Default=00H)..............................................................................29

 

6.1.44

 

RESERVED REGISTER – OFFSET 8AH-9EH.........................................................................................................30

 

6.1.45

 

PIXCLK 0 DELAY REGISTER– OFFSET 9FH(Default=00H) ..............................................................................30

 

6.1.46

 

RESERVED REGISTER – OFFSET A0H-B0H.........................................................................................................30

 

6.1.47

 

CH8IDEN REGISTER – OFFSET B1H(Default=00H) ...........................................................................................30

 

6.1.48

 

RESERVED REGISTER – OFFSET B2H-C7H .........................................................................................................30

 

6.1.49

 

GPIO_0_1 MODE REGISTER– OFFSET C8H(Default=00H)..............................................................................30

 

6.1.50

 

GPIO_2_3 MODE REGISTER– OFFSET C9H(Default=00H)..............................................................................31

 

6.1.51

 

VIDEO OUTPUT MODE REGISTER – OFFSET CAH(Default=00H)...............................................................31

 

6.1.52

 

GPIO POLARITY REGISTER – OFFSET CBH (Default=00H) ............................................................................32

 

6.1.53

 

PIXOUT OUTPUT CH2 SELECT REGISTER – OFFSET CCH (Default=39H)................................................32

 

6.1.54

 

PIXOUT OUTPUT CH1 SELECT REGISTER – OFFSET CDH (Default=E4H) ...............................................32

 

6.1.55

 

RESERVED REGISTER– OFFSET CEH ...................................................................................................................33

 

6.1.56

 

SERIAL MODE CONTROL REGISTER– OFFSET CFH(Default=00H).............................................................33

 

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