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PI3WVR12412 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI3WVR12412 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 13 page  1 www.pericom.com 04/29/14 Features Î Î 4-lane, 1:2 mux/demux that will support RBR, HBR1, or HBR2 Î Î Data rate: 3.4 Gbps to 6.0 Gbps for high data channels Î Î Supports DDC with HPD channel mux/demux @ HDMI Î Î Supports 720 Mbps high-speed DP AUX @ DP Î Î -1.7 dB Insertion Loss for Dx channels @ 3.0 GHz Î Î -3 dB Bandwidth for Dx channels: 4.8 GHz Î Î Return loss for Dx channels @ 3.0 GHz: -16 dB Î Î Low Crosstalk for high speed channels: -25 dB@6.0 Gbps Î Î Low Off Isolation for high speed channels: -22dB@6.0 Gbps Î Î Low channel-to-channel skew, 35ps max Î Î Low Bit-to-Bit Skew, 5ps typ (between '+' and '-' bits) Î Î VDD Operating Range: 3.3V +/-10% Î Î ESD Tolerance: 2kV HBM Î Î Packaging (Pb-free & Green): 42 TQFN (ZHE) Description Pericom Semiconductor’s PI3WVR12412 is a multi-standard vid- eo switch with wide voltage range capability. It supports HDMI 2.0, DisplayPort 1.2, and emerging and proprietary standard. PI3WVR12412 can pass high-speed signals up to 1.2 V peak-to- peak differential with a common-mode voltage from 0 to 3.4V for TMDS signal. The wide voltage range allow DC-coupled multi-standard opera- tion. Eliminating AC coupling capacitors saves board space and improves signal integrity for dense PCB design. The high speed channels can also pass 0V-3.3V CMOS signals up to 1MHz. In addition to four high-speed lanes, PI3WVR12412 also switch- es the DDC and HPD signals or AUX and HPD signals using the DDC/ AUX and HPD channel mux/demux. Application Î Î Routing of HDMI 2.0 video signals with low signal attenuation between source and sink for 4K2K ultra high definition video display and broadcast video equipment. Î Î Routing of DisplayPort video signals with low signal attenuation between source and sink for PC and monitor. Block Diagram PI3WVR12412 HDMI 2.0, DisplayPort 1.2 Video Switch D0+ D0 D1+ D1 D2+ D2- D3+ D3- SCL/ AUX+ SDA/ AUX- HPD D0+A D0 -A D1+A D1 -A D0+B D0-B D1+B D1-B D2+A D2-A D3+A D3-A D2+B D2-B D3+B D3-B - - Logic Control GPU_SEL SCL A/ AUX+ A SDA A/ AUX- A HPD A SCL B/ AUX+ B SDA B/ AUX- B HPD B OE DDC/ AUX_HPD_SEL 14-0056 |
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