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LM98725CCMTX Datasheet(PDF) 11 Page - Texas Instruments |
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LM98725CCMTX Datasheet(HTML) 11 Page - Texas Instruments |
11 / 145 page LM98725 www.ti.com SNAS474H – APRIL 2009 – REVISED MARCH 2015 6.5 AC Timing Specifications The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 27 MHz unless otherwise specified. All other limits TA = 25°C. (1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT INPUT CLOCK TIMING SPECIFICATIONS 27 0.66 (Mode 3) 30 INCLK = PIXCLK (Pixel Rate Clock) 1 MHz (Mode 2) 30 1 (Mode 1) fINCLK Input Clock Frequency 81 2 (Mode 3) 60 INCLK = ADCCLK (ADC Rate Clock) 2 MHz (Mode 2) 30 2 (Mode 1) Tdc Input Clock Duty Cycle 40/60% 50/50% 60/40% FULL CHANNEL LATENCY SPECIFICATIONS 3 Channel Mode Pipeline Delay PIXPHASE0 24 Figure 54 (LVDS) PIXPHASE1 23.5 tLAT3 TADC Figure 59 (CMOS) PIXPHASE2 23 PIXPHASE3 22.5 2 Channel Mode Pipeline Delay PIXPHASE0 21 Figure 55 (LVDS) PIXPHASE1 20.5 tLAT2 TADC Figure 60 (CMOS) PIXPHASE2 20 PIXPHASE3 19.5 1 Channel Mode Pipeline Delay PIXPHASE0 19 Figure 56 (LVDS) PIXPHASE1 18.5 tLAT1 TADC Figure 61 (CMOS) PIXPHASE2 18 PIXPHASE3 17.5 (1) The analog inputs are protected as shown in Figure 2. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the input goes above VA and below AGND. (2) Test limits are specified to AOQL (Average Outgoing Quality Level). (3) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM98725 |
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