3

PS8888A

04/26/07

PI2EQX4432D

2.5Gbps x2 Lane PCI Express Repeater / Equalizer

with Signal Detect and Flow-through Pinout

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Ps

Supply Power

All Enables = LVCMOS High

0.1

W

All Enables = LVCMOS Low

0.6

Latency

From input to output

2.0

ns

CML Receiver Input

Return Loss

50 MHz to 1.25 GHz

12

dB

Differential Input Peak-to-

peak Voltage

0.175

1.200

V

AC Peak Common Mode

Input Voltage

150

mV

Signal Detect Threshold

EN_x = High

120

175

mV

DC Differential Input

Impedance

80

100

120

Ω

DC Input Impedance

40

50

60

Equalization

Total Jitter

0.3

Ulp-p

Deterministic jitter

0.2

1.5

psrms

Storage Temperature........................................................ –65°C to +150°C

Supply Voltage to Ground Potential................................... –0.5V to +2.5V

Current Output ................................................................-25mA to +25mA

Power Dissipation Continous ......................................................... 800mW

Operating Temperature.............................................................. 0 to +70°C

Note:

Stresses greater than those listed under MAXIMUM RAT-

INGS may cause permanent damage to the device. This is

a stress rating only and functional operation of the device

at these or any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may affect reliability.

Maximum Ratings

(Above which useful life may be impaired. For user guidelines, not tested.)

Output Swing Control

SEL–OL_[A:D]

Output Swing

01x

1

1.2x

Equalizer Selection

SEL−EQ_[A:D]

Compliance Channel

0

[0:2.5dB] @ 1.25 GHz

1

[0:6.5dB] @ 1.25 GHz

Output De-emphasis Adjustment

SEL−DE_[A:D]

De-emphasis

0

0dB

1

–3.5dB

24

IREF

I

Connect to 475-Ohm resistor to ground when the reference clock is used. Otherwise

do not connect.

3, 6, 9, 12, 28, 31,

34, 37, 48

VDD

PWR

1.8V Supply Voltage

25, Center Pad

GND

PWR

Supply Ground, Center pad must be connected

Notes

1.

K28.7 pattern is applied differentially at point A as shown in Figure 1.

2.

Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum

deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or

equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or

its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at

0V at point C of Figure 1.

07-0106